External interrupt (INT) at HC12

[Svenh]

Hi @all,

I have a question regarding the handling of (external) interrupts (e.g. IRQ) if the (maskable) interrupts are localy enabled (e.g. IRQCR) and globaly disabled via the I-bit in CCR.

As far as I understand an occuring interrupt will pend until the global interrupts enabled again via the I-bit in CCR. Is that correct?

For the external interrupt (IRQ) no "flag" is implemented. Thus I'm not sure what happen if the external interrupt (IRQ) occurs while global interrupt disabled. So if the IRQ is configured as edge-sensitive the edge-detecting latch will most likely cause also a pending interrupt that will be handeled after the global interrupt enabled again. Is that right? What happens with an level-sensitive interrupt that occurs and disappears (IRQ goes low and high again) while global interrupts disabled? The interrupt is also pending or will it be lost?

Thanks in advance,
Sven

[kef]

Hi

It's a good question, especially regarding edge sensitive IRQ.

I had no doubt that level-sensitive IRQ will be not pending if /IRQ pin is pulled low, then puled high while interrupts are disabled (CCR I bit is set). External devices are assumed to hold /IRQ pin low until MCU services it.

I tried to check on MC9S12XD256 if edge-sensitive IRQ will or won't get pending if pulsing /IRQ pin low while interrupts are disabled. I connected IRQ pin to PORTB pin; set PORTB pin high; configured IRQ mode to edge-sensitive (IRQCR=0xC0; set PORTB pin (and /IRQ pin) low, then high; wait quite a long, then enabled interrupts. Results are edge sensitive IRQ gets pending pulsing /IRQ pin low while interrupts are disabled. I wonder what is the mechanism or resetting edge-sensitive IRQ latch. It must be not just "falling" or "rising edge" of CCR I-bit, it must be well more complicated...

[dkelly]

---

kef wrote:

I wonder what is the mechanism or resetting edge-sensitive IRQ latch. It must be not just "falling" or "rising edge" of CCR I-bit, it must be well more complicated...

---

Lets wake this thread up as it most closely resembles my problem today.

Am using the external IRQ through a buffer to synchronize with AC power. Sometimes with a little bit of noise on the power lines I get an extra pulse before the next clean falling edge.

What I have attempted was to set timer 7 for 1.5 milliseconds from within my IRQ service routine, disable external IRQ, enable timer 7 IRQ. Then when timer 7 fires disable timer 7 IRQ and enable external IRQ. Problem is that if there was a falling edge on external IRQ during that 1.5 MS the external IRQ service routine executes on exit from the timer 7 routine.

So, "How does one clear a pending external IRQ without actually vectoring through the service routine?" Isn't the toggle of the CCR I bit as that happens on exit from my timer 7 routine where external IRQ is enabled, then promptly vectors to the external IRQ routine on RTI from timer 7.

Would really rather not have to compare elapsed time in my external IRQ in order to discard false inputs altho am already doing that to ensure we're seeing good clean power.

[Svenh]

Hi,

thanks for your experiment and answer.

Your described behavior for the edge-sensitive interrupt confirms my thought about the edge-sensitive interrupt. The mechanism of reseting the IRQ latch is also not clear to me but it doesn't matter and at least it works (I think in interaction with the interrupt vector table and appropriated ISR).

More questionable is the handling of the level-sensitive IRQ. What happens if the /IRQ is configured as level-sensitive (low) and enabled but the global interrupts are disable (via I-bit). An short low level at /IRQ will also cause a pending IRQ? Or will this short low level at /IRQ be lost? In the documentation only a latch for the edge-sensitive IRQ is mentioned.

[kef]

Hi,

I verified level-sensitive IRQ too. Level sensitive IRQ isn't latched. /IRQ pulse low event is lost if it happens while interrupts are disabled. /IRQ=low condition must continue until I-bit is cleared and no higher than IRQ priority interrupts are pending...

I regret doc's don't explain how edge-sensitive IRQ latch is cleared. Couldn't something like S12X spurious interrupt clear it? Undocumented, so unreliable a bit :smileysad:.

Regards

[Svenh]

Unfortunately I'm not familar with 12X family and don't know anything about spurious interrupt(s).

Thank you very much for your help in experiments and answers.

Regards,

Sven