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Posted: Wed Jul 27, 2005 9:08 pm
I've been working with the ATD module and have been noticing that the analog to digital conversion is not entirely linear. There digital output seems to get stuck at certain values regardless of the increasing analog voltages. For example, at approximately 1.3 V, the digital output is 255. However, the digital output remains at 255 until an analog voltage of approximately 1.5 V. At 1.5 V, the digital value jumps to 304. There are a number of these traps, or flat sections in the digital output despite increasing voltages. They occur at almost exact multiples of 64. The traps occur at 127, 255, 319, 384, 448, 575, 639, 768, and 831.
What is the reason for the nonlinearity at these points?
Why is there a pattern to where the traps occur (multiples of 64)?
What is causing the traps?
Are there any other products I should consider that would have more accurate analog to digital conversion?
Posted: Wed Jul 27, 2005 10:06 pm
I would guess your software is incorrect. I have used the A/D on various versions of the 9s12 and 6811 and never had any trap or nonlinearity problems.
What is your reference voltage? If it is Vcc then the 255 output for a 1.3V input is a big clue that your byte alignment is wrong or you are reading the wrong register.
Posted: Thu Jul 28, 2005 2:03 pm
My reference voltage is Vcc. I am reading the ATDDROH register, which is the conversion result register for pin 0. How could I test if my byte alignment is correct? As far as I know, it is, but how can I be sure? What does the pattern of traps at multiples of 64 indicate?
Posted: Thu Jul 28, 2005 2:21 pm
I found the atd low noise. I have of cause taken the precaution of adding a 1K or 10K resistor in series with each input plus a 100n from the input to 0V. I have also got a 1K in series with Ref. high and a 100n to 0V. The only thing I have not discovered in data sheets is what is the atd input current is to calculate the error the series resistors introduce.
Posted: Tue Aug 2, 2005 6:45 pm
It turns out that I was setting the prescaler value in ATDCTL4 to 0 for a bus clock frequency min-max of 1-4 MHz and this was causing a problem. I changed the prescalers to 5 (%00101) for a min-max of 6-24 MHz and then the ATD accuracy was almost perfect.
