p2041rdb

[hv]

Is there an errata on the CPLD for the P2041RDB-PC?  The power on these are not reliable.  after turning on/off a few times, the power wouldn't come on again.  It seemed like the machine was in a strange state until I pushed and held the power button and unplugged the power cord then the power button would work again.

I didn't observe this behavior when using the P2041RDB-PB.  

Is it possible to replace the CPLD for the P2041RDB-PC with the CPLD for the P2041RDB-PB?  If yes, how can I do that?  

Thanks!

[ufedor]

Please provide U-Boot booting logs for both boards for inspection.

[hv]

Here’s the uboot log for the P2041RDB-PC

** FROM P2041RDB-PC**********************************************

U-Boot 2013.01-00115-g831b30d (Jun 15 2013 - 05:53:49)

CPU0:  P2041E, Version: 2.0, (0x82180120)

Core:  E500MC, Version: 3.2, (0x80230032)

Clock Configuration:

       CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz,

       CCB:750  MHz,

       DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:93.750 MHz

       FMAN1: 583.333 MHz

       QMAN:  375 MHz

       PME:   375 MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

Reset Configuration Word (RCW):

       00000000: 12600000 00000000 241c0000 00000000

       00000010: 248e40c0 c3c02000 de800000 40000000

       00000020: 00000000 00000000 00000000 d0030f07

       00000030: 00000000 00000000 00000000 00000000

Board: P2041RDB, CPLD version: 4.1 vBank: 1

SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz

I2C:   ready

SPI:   ready

DRAM:  Initializing....using SPD

Detected UDIMM

2 GiB left unmapped

4 GiB (DDR3, 64-bit, CL=9, ECC off)

       DDR Chip-Select Interleaving Mode: CS0+CS1

Testing 0x00000000 - 0x7fffffff

Testing 0x80000000 - 0xffffffff

Remap DDR 2 GiB left unmapped

POST memory PASSED

Flash: 128 MiB

L2:    128 KB enabled

Corenet Platform Cache: 1024 KB enabled

SERDES: bank 3 disabled

SRIO1: disabled

SRIO2: disabled

NAND:  512 MiB

MMC:  FSL_SDHC: 0

EEPROM: Invalid ID (ff ff ff ff)

PCIe1: disabled

PCIe2: Root Complex, x1, regs @ 0xfe201000

  01:00.0     - 104c:823e - Bridge device

   02:00.0    - 104c:823f - Serial bus controller

PCIe2: Bus 00 - 02

PCIe3: disabled

In:    serial

Out:   serial

Err:   serial

Net:   Initializing Fman

Fman1: DTSEC3 set to unknown interface 12

Fman1: Uploading microcode version 106.1.9

PHY reset timed out

FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC4, FM1@DTSEC5, FM1@TGEC1

***************************************************************

And here’s the uboot log from P2041RDB-PB

** from P2041RDB-PB **

U-Boot 2011.12-00025-gc6d9d50 (Oct 24 2012 - 04:48:58)

CPU0:  P2041E, Version: 1.1, (0x82180111)

Core:  E500MC, Version: 2.2, (0x80230022)

Clock Configuration:

       CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz,

       CCB:750  MHz,

       DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:93.750 MHz

       FMAN1: 583.333 MHz

       PME:   375 MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

Board: P2041RDB, CPLD version: 4.1 vBank: 0

36-bit Addressing

Reset Configuration Word (RCW):

       00000000: 12600000 00000000 241c0000 00000000

       00000010: 648ea0c1 c3c02000 de800000 40000000

       00000020: 00000000 00000000 00000000 d0030f07

       00000030: 00000000 00000000 00000000 00000000

SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz

I2C:   ready

SPI:   ready

DRAM:  Initializing....using SPD

Detected UDIMM UG51U6400N8SU-ACF

2 GiB left unmapped

4 GiB (DDR3, 64-bit, CL=9, ECC off)

       DDR Chip-Select Interleaving Mode: CS0+CS1

Testing 0x00000000 - 0x7fffffff

Testing 0x80000000 - 0xffffffff

Remap DDR 2 GiB left unmapped

POST memory PASSED

Flash: 128 MiB

L2:    128 KB enabled

Corenet Platform Cache: 1024 KB enabled

SERDES: bank 3 disabled

SRIO1: disabled

SRIO2: disabled

NAND:  512 MiB

MMC:  FSL_SDHC: 0

EEPROM: Invalid ID (ff ff ff ff)

PCIe1: disabled

PCIe2: Root Complex, x1, regs @ 0xfe201000

  01:00.0     - 104c:823e - Bridge device

   02:00.0    - 104c:823f - Serial bus controller

PCIe2: Bus 00 - 02

PCIe3: disabled

In:    serial

Out:   serial

Err:   serial

Net:   Initializing Fman

Fman1: Uploading microcode version 106.1.4

FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5

[ufedor]

From the provided logs it is clear that both boards have the same CPLD version - 4.1

[hv]

I was thinking it’s the CPLD…but if not the CPLD then what could be causing the difference?

Thanks!

[hv]

Is there a way we can replace the CPLD for the P2041RDB-PC with the version from the P2041RDB-PB?

Thanks!