We have a custom board built around a T4240 and are having some trouble getting the DDR up to speed. A handful of questions regarding the T4240's DDR and the QorIQ configuration suite DDR validation tool:
Thanks
See comments from tools expert:
I confirm that T4240 is supported in QCS 3.0.5 and DDRv 2.0.2
For devices >=P2040 the centering the clock is optimized meaning we do not do a full variation.
Customer should be fine with the values after running both tables.
Do you uses the Read from SPD wizard option? Using that option would ensure that DDR is being configured with the vendor optimal settings stored in SPD. I strongly encourage to use that option.
Thank you for your replies.
We aren't using SPD, since we are using multi-chip modules that do not include SPD EEPROMs.
Using the values calculated in the DDRv tool, we were able to bring DDR up to full speed.Thank you!
1. T4240 is supported by DDRV;
2. There are two tables for CLK_ADJ. First table is made for discover very rapid some combinations of CLK_ADJ, WRLVL_START, which are working on board. And the second table is somehow a fine-tuning for CLK_ADJ.
3. When working combination of CLK_ADJ, WRLVL_STAR are discovered, the rest of the cells will skipper and tests in the second table is started.
Adrian
3. You can also see from the attached screenshot that it's not running the whole test matrix -- why not? How can we get it to run the whole test matrix?
If I understand you correctly, this is choose from the upper right of the window, click select all cells button.