T1042 read failed in memory map

[insunghwang]

hi all

I am trying to setup custom board based T1042.

The following memory map is desired:

DDR	0_0000_0000 - 0_3FFF_FFFF (1G)
NAND	b_4000_0000 - b_7FFF_FFFF (1G)	CS1
SLOT	a_4000_0000 - a_BFFF_FFFF (2G)	CS3
NOR	f_E800_0000 - f_E9FF_FFFF (32M)	CS0
CPLD	f_F900_0000 - f_FAFF_FFFF(32M)	CS2
CCSR	f_FE00_0000 - f_FEFF_FFFF(16M)
DCSR	f_F000_0000 - f_F003_FFFF(4M)
B MAN	f_FF40_0000 - f_FF5F_FFFF(32M)
Q MAN	f_FF60_0000 - f_FF7F_FFFF(32M)

Machine check error when reading 0xa80000000 in slot area (machine check error does not appear when reading 0xa4000_0000 ~ 0xa7000_0000)

=> md.w 0xa60000000
60000000: 6000 6000 6000 6000 6000 6000 6000 6000 `.`.`.`.`.`.`.`.
60000010: 6000 6000 6000 6000 6000 6000 6000 6000 `.`.`.`.`.`.`.`.
60000020: 6000 6000 6000 6000 6000 6000 6000 6000 `.`.`.`.`.`.`.`.
60000030: 6000 6000 6000 6000 6000 6000 6000 6000 `.`.`.`.`.`.`.`.
60000040: 6000 6000 6000 6000 6000 6000 6000 6000 `.`.`.`.`.`.`.`.
60000050: 6000 6000 6000 6000 6000 6000 6000 6000 `.`.`.`.`.`.`.`.
60000060: 6000 6000 6000 6000 6000 6000 6000 6000 `.`.`.`.`.`.`.`.
60000070: 6000 6000 6000 6000 6000 6000 6000 6000 `.`.`.`.`.`.`.`.
=> md.w 0xa70000000
70000000: 7000 7000 7000 7000 7000 7000 7000 7000 p.p.p.p.p.p.p.p.
70000010: 7000 7000 7000 7000 7000 7000 7000 7000 p.p.p.p.p.p.p.p.
70000020: 7000 7000 7000 7000 7000 7000 7000 7000 p.p.p.p.p.p.p.p.
70000030: 7000 7000 7000 7000 7000 7000 7000 7000 p.p.p.p.p.p.p.p.
70000040: 7000 7000 7000 7000 7000 7000 7000 7000 p.p.p.p.p.p.p.p.
70000050: 7000 7000 7000 7000 7000 7000 7000 7000 p.p.p.p.p.p.p.p.
70000060: 7000 7000 7000 7000 7000 7000 7000 7000 p.p.p.p.p.p.p.p.
70000070: 7000 7000 7000 7000 7000 7000 7000 7000 p.p.p.p.p.p.p.p.
=> md.w 0xa80000000
80000000:Machine check in kernel mode.
Caused by (from mcsr): mcsr = 0x0000a000
NIP: 3FF5AE2C XER: 00000000 LR: 3FF5ADE4 REGS: 3faddb40 TRAP: 0200 DAR: 00000000
MSR: 00029200 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 3FF5ADE4 3FADDC30 3FADDEF8 00000009 0000003A 00000030 00000020 FFFFFFFE
GPR08: 3FADDC38 00000020 80000000 3FADDC30 3FEEF82C 00000000 00000008 00000000
GPR16: 00000002 3FF7910C 00000000 0000002E FFFFFF97 3FF633A4 3FF70C64 3FF79104
GPR24: 3FF685B4 00000005 00000004 80000000 80000000 00000040 3FF7E77C 00000008
MCSR=0x0000a000 MCSRR0=0x3ff5ae2c
MCSRR1=0x00029200 MCAR=0x00000000
Call backtrace:
3FF5ADE4 3FEEF878 3FF10F04 3FF00EAC 3FF0166C 3FF0171C 3FF0F880
3FEFF010 3FF01FEC 3FF539F8 3FF023D8 3FEE1050
Returning back to 0x3ff5ae2c
Machine check in kernel mode.

Any ideas about why the machine check error ?

it is reg info in u-boot

entry 00: V: 1 EPN 0xfffff000 RPN 0x3ffff000 size:4 KiB
entry 01: V: 1 EPN 0xfe000000 RPN 0xffe000000 size:16 MiB
entry 02: V: 1 EPN 0xe0000000 RPN 0xfe0000000 size:256 MiB
entry 03: V: 1 EPN 0x00000000 RPN 0x00000000 size:1 GiB
entry 04: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 05: V: 1 EPN 0xf4000000 RPN 0xff4000000 size:16 MiB
entry 06: V: 1 EPN 0xf5000000 RPN 0xff5000000 size:16 MiB
entry 07: V: 1 EPN 0xf6000000 RPN 0xff6000000 size:16 MiB
entry 08: V: 1 EPN 0xf7000000 RPN 0xff7000000 size:16 MiB
entry 09: V: 1 EPN 0xf0000000 RPN 0xf00000000 size:4 MiB
entry 10: V: 1 EPN 0x40000000 RPN 0xb40000000 size:64 KiB
entry 11: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 12: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 13: V: 0 EPN 0xfe000000 RPN 0xffe000000 size:1 MiB
entry 14: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB
entry 15: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB
entry 16: V: 1 EPN 0x40000000 RPN 0xb40000000 size:1 GiB
entry 17: V: 1 EPN 0x40000000 RPN 0xa40000000 size:1 GiB
entry 18: V: 1 EPN 0x80000000 RPN 0xa80000000 size:1 GiB
entry 19: V: 1 EPN 0xf9000000 RPN 0xaf9000000 size:16 MiB
entry 20: V: 1 EPN 0xfa000000 RPN 0xafa000000 size:16 MiB
entry 21: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 22: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 23: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 24: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 25: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 26: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 27: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 28: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 29: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 30: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 31: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 32: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 33: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 34: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 35: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 36: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 37: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 38: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 39: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 40: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 41: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 42: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 43: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 44: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 45: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 46: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 47: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 48: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 49: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 50: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 51: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 52: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 53: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 54: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 55: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 56: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 57: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 58: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 59: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 60: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 61: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 62: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 63: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB

Local Access Window Configuration
LAWBARH00: 0x0000000f LAWBARL00: 0xe8000000 LAWAR00: 0x81f00018
(EN: 1 TGT: 0x1f SIZE: 32 MiB)
LAWBARH01: 0x0000000f LAWBARL01: 0xf4000000 LAWAR01: 0x81800018
(EN: 1 TGT: 0x18 SIZE: 32 MiB)
LAWBARH02: 0x0000000f LAWBARL02: 0xf6000000 LAWAR02: 0x83c00018
(EN: 1 TGT: 0x3c SIZE: 32 MiB)
LAWBARH03: 0x0000000a LAWBARL03: 0xf9000000 LAWAR03: 0x81f00018
(EN: 1 TGT: 0x1f SIZE: 32 MiB)
LAWBARH04: 0x0000000f LAWBARL04: 0x00000000 LAWAR04: 0x81d00015
(EN: 1 TGT: 0x1d SIZE: 4 MiB)
LAWBARH05: 0x0000000b LAWBARL05: 0x40000000 LAWAR05: 0x81f0001d
(EN: 1 TGT: 0x1f SIZE: 1 GiB)
LAWBARH06: 0x0000000a LAWBARL06: 0x40000000 LAWAR06: 0x81f0001e
(EN: 1 TGT: 0x1f SIZE: 2 GiB)
LAWBARH07: 0x00000000 LAWBARL07: 0x00000000 LAWAR07: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH08: 0x00000000 LAWBARL08: 0x00000000 LAWAR08: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH09: 0x00000000 LAWBARL09: 0x00000000 LAWAR09: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH10: 0x00000000 LAWBARL10: 0x00000000 LAWAR10: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH11: 0x00000000 LAWBARL11: 0x00000000 LAWAR11: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH12: 0x00000000 LAWBARL12: 0x00000000 LAWAR12: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH13: 0x00000000 LAWBARL13: 0x00000000 LAWAR13: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH14: 0x00000000 LAWBARL14: 0x00000000 LAWAR14: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH15: 0x00000000 LAWBARL15: 0x00000000 LAWAR15: 0x8100001d
(EN: 1 TGT: 0x10 SIZE: 1 GiB)
IFC Controller Registers
CSPR0:0xE8000101 AMASK0:0xFE000000 CSOR0:0x0000000C
IFC_FTIM0:0x40050005
IFC_FTIM1:0x35001A13
IFC_FTIM2:0x0410381C
IFC_FTIM3:0x00000000
CSPR1:0x40000083 AMASK1:0xC0000000 CSOR1:0x8510A100
IFC_FTIM0:0x0E18070A
IFC_FTIM1:0x32390E18
IFC_FTIM2:0x01E0501E
IFC_FTIM3:0x00000000
CSPR2:0xF9000105 AMASK2:0xFE000000 CSOR2:0x00000000
IFC_FTIM0:0xE00E000E
IFC_FTIM1:0x0E001F00
IFC_FTIM2:0x0E20001F
IFC_FTIM3:0x00000000
CSPR3:0x40000105 AMASK3:0x80000000 CSOR3:0x00000000
IFC_FTIM0:0xE00E000E
IFC_FTIM1:0x0E001F00
IFC_FTIM2:0x0E20001F
IFC_FTIM3:0x00000000
CSPR4:0x00000000 AMASK4:0x00000000 CSOR4:0x0000000C
IFC_FTIM0:0x00000000
IFC_FTIM1:0x00000000
IFC_FTIM2:0x00000000
IFC_FTIM3:0x00000000
CSPR5:0x00000000 AMASK5:0x00000000 CSOR5:0x0000000C
IFC_FTIM0:0x00000000
IFC_FTIM1:0x00000000
IFC_FTIM2:0x00000000
IFC_FTIM3:0x00000000
CSPR6:0x00000000 AMASK6:0x00000000 CSOR6:0x0000000C
IFC_FTIM0:0x00000000
IFC_FTIM1:0x00000000
IFC_FTIM2:0x00000000
IFC_FTIM3:0x00000000
CSPR7:0x00000000 AMASK7:0x00000000 CSOR7:0x0000000C
IFC_FTIM0:0x00000000
IFC_FTIM1:0x00000000
IFC_FTIM2:0x00000000
IFC_FTIM3:0x00000000

[ufedor]

In Power Architecture it is required to align base address of a window to its size.

Thus, a_4000_0000 is not a correct address for the 2G window.

Possible correct addresses are:

a_0000_0000

a_8000_0000