T1042 freeze after 32bit PCIE write

[wengangzhu]

Broadcom switch is connected to t1042 by PCIe on our card. Broadcom switch is working with PCIe EP mode. Broadcom switch can be scanned and bootloader image download from cpu to switch successfully. But after download, t1042 freeze after 32bit pcie write suddenly. I cannot input anything from t1042 console and nothing printed on console. It needs power cycle to recover the system.

uboot and linux kernel code are built from yocto. linux kernel version is 4.14.47.

Is there any way to debug such issue? Can we trigger a PCIe exception or crash? thanks.

[wengangzhu]

I cannot provide RESET_REQ_B info because of remoting debugging. t1042 pcie information was attached. Please guide me what's the LAWs and ATMUs register address needed to dump if dump info is wrong. thanks.

[ufedor]

LAWs:

QorIQ T1040 Reference Manual, 2.4 Local Access Window (LAW) Memory Map

Outbound ATMUs:

QorIQ T1040 Reference Manual, 28.6 PCI Express memory-mapped registers, offset range 24_0C00 - 24_0C90

[wengangzhu]

please see attachment t1042_pcie_info.log. it contains LAWs and ATMUs.

[ufedor]

Please provide log of the problem command.

[wengangzhu]

No command. cpu freeze after 32bit pcie write.

Before cpu freeze, bootloader firmware(size=69K) is downloaded from cpu to broadcom switch by PCIe successfully. then start to download ddr phy image(size=160K). ddr phy image is divided 8 segments. each segment size is 20K. the first segment is downloaded and checked successfully. But cpu freeze after download second segment, then issue 32bit pcie write register to report second segment writing complete. 

[ufedor]

Please use a debugger to determine which exactly instruction causes the processor's hang.

[wengangzhu]

Do you mean to use jtag? Is any document to describe how to debug? thanks.

[ufedor]

If you have a JTAG debugger, then debugging technique is described in its documentation - for example CodeWarrior Development Studio for Power Architecture Processors Targeting Manual.

Ensure that the procedure used for uploading data to the PCIe switch is correct.

[wengangzhu]

thank you.

[ufedor]

1) How RESET_REQ_B behaves when the freeze happens?

2) You wrote:

> t1042 freeze after 32bit pcie write

Do you mean that T1042 as RC performs write operation to a PCIe EP using an Outbound ATMU window?

Please provide as textual attachments raw memory dumps (captured by U-Boot "md" command) for the T1042:

a) all LAWs

b) all PCIe Outbound ATMUs