On our custom T8021 board we have a registered DDR3 SDRAM connected to the CPU. We have successfully validated the timings for 400 MHz DDR clock and 800 MHz clock settings. For the 400 MHz all smoke tests pass. For the 800MHz setting the DMA test fails. The log of this test is attached. Also a register dump of the measurements with 800MHz is attached.
U-Boot is booting up correctly with both settings, however I think that it uses burst mode but does not setup a DMA transfer as the test does?
What does the test actually test?
Could this be rooted in still incorrect settings?
Original Attachment has been moved to: dma_test_800MHz_log.txt.zip
Original Attachment has been moved to: T2081_v1_1_annotated_hex_ecc.txt.zip
> For the 400 MHz all smoke tests pass.
What is the DMA test result in this case?
> What does the test actually test?
Please refer to the QCVS DDR Tool User Guide, 1.2.3.3 Using read/write data bus margin scenario.
Please provide screenshot of the DMA test failure.
The DMA test for the 400MHz case passes (1/1 runs as is the default). For the 800MHz timing I have increased the amounts of test runs but they fail. The logs of that failure correspond to the one I have attached to the original post. Please find a screenshot of another try attached to this post.
Is there any additional information I can provide?