PARALLEL FLASH INTERFACING IN MPC8309TOWER BOARD

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PARALLEL FLASH INTERFACING IN MPC8309TOWER BOARD

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santhoshmunagal
Contributor I

Hi everyone this is Santhosh. 

I was a hardware designer and currently working on MPC8309 PROCESSOR. When I was going through the HARDWARE DESIGN CHECKLIST of MPC8309 I have noticed one thing that in order to interface a parallel flash of NOR type the address line LA[25] is normally not required if the device data width is 16 bits.

My questions are:

   1.What is the relation between the address lines and data bus width?

   2.Why the address line LA[24] in MPC8309 has to be connected to A[0] of NOR FLASH ? Is this related to                    ENDIANNESS? If so please explain

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alexander_yakov
NXP Employee
NXP Employee

1. From the processor side, each address value addresses one byte. That is, you have one byte at address 0, one byte at address 1 and so on. From the flash side, for 16-bit flash each address in flash addresses one 16-bit value, this is two bytes. To connect this flash, least significant address of the processor is left unconnected, address bus is connected with a shift.

2. LA[24] is least significant. This is not "endianess", but different numbering scheme of address lines.

Have a great day,
Alexander

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santhoshmunagal
Contributor I

Thanks alexander

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