Mode Registers!

[qammarabbas]

Hi,

While configuring the registers of T1042 for the DDR memory controller, i encountered a field "UNQ_MRS_EN" in the DDR_DDR_SDRAM_CFG_2 register and i am unable to comprehend what does it mean. Can anybody please explain what is it for and when to use it?

[ufedor]

Please refer to the QorIQ T1040 Reference Manual, 14.4 DDR Memory Map/Register Definition.

If DDR_DDR_SDRAM_CFG_2[UNQ_MRS_EN]=0 then for all chip selects data from the following MODE registers will be used:

DDR_DDR_SDRAM_MODE

DDR_DDR_SDRAM_MODE_2

DDR_DDR_SDRAM_MODE_9

DDR_DDR_SDRAM_MODE_10

If DDR_DDR_SDRAM_CFG_2[UNQ_MRS_EN]=1 then individual data from the following MODE registers will be used:

for CS0:

DDR_DDR_SDRAM_MODE

DDR_DDR_SDRAM_MODE_2

DDR_DDR_SDRAM_MODE_9

DDR_DDR_SDRAM_MODE_10

for CS1:

DDR_DDR_SDRAM_MODE_3

DDR_DDR_SDRAM_MODE_4

DDR_DDR_SDRAM_MODE_11

DDR_DDR_SDRAM_MODE_12

for CS2:

DDR_DDR_SDRAM_MODE_5

DDR_DDR_SDRAM_MODE_6

DDR_DDR_SDRAM_MODE_13

DDR_DDR_SDRAM_MODE_14

for CS3:

DDR_DDR_SDRAM_MODE_7

DDR_DDR_SDRAM_MODE_8

DDR_DDR_SDRAM_MODE_15

DDR_DDR_SDRAM_MODE_16

[qammarabbas]

Could you please elaborate when to enable this bit and when to clear? Thank you!

[ufedor]

It is up to the board designer.

[qammarabbas]

what information does the board designer need to know before setting/clearing this bit?