Failed during read PCIe controller address on T2080QDS

[minghu_du]

LAW Config: PCIe0  --- 0xf80000000

Core hang during read address 0xf80000000. It looks like an unrecoverable error while accessing the address.

[minghu_du]

Root Cause :

OB_CK bit of PCI Express Configuration Register (PEX_CONFIG offset is 0x14)  was not set.

[ufedor]

It is normal that Machine Check is generated when a PCIe read transaction addressed memory region assigned to a target device which is not present.

In this case no valid data can be returned, so asynchronous Machine Check is generated.

> What is the correct CPU response when accessing 0xf80000000?

What is mapped to this address?

Please provide U-Boot booting log.

[minghu_du]

ufedor, Thanks for your replay!

>What is mapped to this address?

I just specify the address 0xf80000000(it could be any other address) as PCIe space through LAW and no real PCIe device assigned to this address.

> What is the correct CPU response when accessing 0xf80000000?

Not clear, I'm asking for this because I caught the machine check exception on T2080RDB CPU version 1.1 but CPU hanged on T2080RDB CPU version 1.0, T2080QDS and T4240QDS.

>In this case no valid data can be returned, so asynchronous Machine Check is generated.

I think this is the real reason for this problem,  accessing the PCIe address without a hardware populated may cause an asynchronous MCK.

And does the asynchronous MCK will cause CPU to hang?

[ufedor]

> And does the asynchronous MCK will cause CPU to hang?

Please use a debugger to determine what the processor is doing during the hang state.

Please consider that it could be a read instruction which can't be completed because a valid data is not provided.

[minghu_du]

• >Please use a debugger to determine what the processor is doing during the hang state.

• I have done that before and that is why i have posted this question page. When a load assembly instruction "lwz r6,0(r5)" (reading address 0xf80000000)was executed, the CodeWarrior TAP was disconnected and the value of registers MSR/MCSR and other status registers changed to meaningless. And the core has no response anymore.

• However thanks for your replay.