Dual die Nand flash interface with T2080

[rajeshsubramani]

Hi,

I am using T2080 in my application, I planned to interface a following MT29F64G08AFAAAWP-ITZ:A  NAND memory to the IFC bus of T2080. My NAND memory has dual die & which is supporting two chips select pins & two redy/busy pins how to interface this device with T2080  ? clarifications is required on pinout mappings.

Note: FPGA is planned to use for level translation 1.8v to 3.3V

Regards,

Rajesh.S

[LPP]

Dual die NAND memory with separate chip selects and R/B signals can be controled by two IFC memory banks.

Connections are quite straigtforward (banks CS1# and CS2# are assumed).

IFC_CS1#    CE#  

IFC_CS2#    CE2#

IFC_RB1#    R/B# //pullup to OVDD

IFC_RB2#    R/B2# //pullup to OVDD

IFC_CLE        CLE

IFC_ALE        ALE

IFC_WE0#    WE#

IFC_OE#        RE#

IFC_AD[0:7]    DQ[7:0] //reversed

IFC_WP1#    WP# //TSOP package provides single WP signal, other

            //packages provide separate WP signals.

Note1: 1.8v to 3.3V level translation is not shown.

Note2: Some signals have special requirments (IFC_WE0, IFC_OE, IFC_WP0 nust not be pulled down during reset). See datasheet Table 1 for details.

Note3: IFC_AD[0:7] buffer should be controlled by IFC_TE (enable) and IFC_BCTL (direction) signals.

Have a great day,
Pavel

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[rajeshsubramani]

Hi,

Thanks for the update, In my case I am using CS3# & CS4# for the NAND flash(CS 0:2 is assigned for NOR flash & FPGA) then shall I use IFC_RB3# & IFC_RB4# ?

Regards,

Rajesh

[LPP]

Please, refer to T2080RM Sections 13.2.1.1 and 13.2.1.2

T2080 provides four signals RB[0:3]#. RB3# combines protection for chip selects 3-7.

In your case, CS3 and CS4 will share the same signal RB3#.

If you want higher performance solution then it is preferable to allocate CS[2:3] for NAND and move FPGA to CS4.

Have a great day,
Pavel

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