Device Tree Address Ranges for NOR, NAND & CPLD

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Device Tree Address Ranges for NOR, NAND & CPLD

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EmbEng
Contributor III

I am trying to understand following part of device tree generated with T1042D4RDB kernel image:

localbus@ffe124000 {
        reg = <0xf 0xfe124000 0x0 0x2000>;
        ranges = <0x0 0x0 0xf 0xe8000000 0x8000000
                  0x2 0x0 0xf 0xff800000 0x10000
                  0x3 0x0 0xf 0xffdf0000 0x8000>;
        #address-cells = <0x2>;
        #size-cells = <0x1>;
        compatible = "fsl,ifc", "simple-bus";
        interrupts = <0x19 0x2 0x0 0x0>;

        nor@0,0 {
            #address-cells = <0x1>;
            #size-cells = <0x1>;
            compatible = "cfi-flash";
            reg = <0x0 0x0 0x8000000>;
            bank-width = <0x2>;
            device-width = <0x1>;
        };

        nand@2,0 {
            #address-cells = <0x1>;
            #size-cells = <0x1>;
            compatible = "fsl,ifc-nand";
            reg = <0x2 0x0 0x10000>;
        };

        cpld@3,0 {
            compatible = "fsl,t1040d4rdb-cpld", "fsl,deepsleep-cpld";
            reg = <0x3 0x0 0x300>;
        };
    };

Now I have following questions regarding above snippet:

1.  From the ranges property of localbus node, we can see that NOR, NAND and CPLD are mapped to parent's physical addresses 0xfe8000000, 0xfff800000 & 0xfffdf0000 respectively. Where do we get these parent's addresses from?

2.  Relating to first question, if I want to add 3 NOR flashes (replacing NAND and CPLD) on my custom board, what parent addresses will I use for them?

3.  NOR flash on RDB is 256MB and NAND flash is 1GB, then why the size in ranges property is 0x8000000 (128MB) for NOR and 0x10000 (64KB) for NAND flash?

4.  Ranges property of the localbus node shows that the NOR, NAND and CPLD are on chip selects 0, 2 and 3 respectively, but the schematic of RDB shows that the NOR, NAND and CPLD are connected to chip selects 0,1 & 2. Why is this discrepancy?

Can someone clarify my confusions over these queries?

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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

1. It is mapped to the T1042 phyical address space (see section 2.1 Memory Map Overview in the T1040 reference manual). The IFC registers base adrress is CCSRBAR(=0xffe000000)+0x124000 in this space (@ffe124000).

2. You should find unused memory regions in the T1042 phyical address space for each NOR flash.

3. The NOR flash (JS28F00AM29EWHA 128MB) is mapped directly to the T1042 phyical address space, while the NAND is not mapped. Read and write accesses to IFC banks controlled by NAND FCM do not access attached NAND flash EEPROMs directly. Rather, these accesses read and write the buffer RAM (a single, shared 16 KB space internal to the IFC and mapped by the base address of every NAND FCM bank). Minimal IFC bank size is 64 KB; it covers that 16 KB buffer.

4. There is definetely discrepancy. May be schematics or DTS is wrong. Notice that NAND can be probed when no match is found for a chip select's DTS-defined address base. See patch
https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-August/120311.html

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734 Views
EmbEng
Contributor III

Just another query please, why my T1042D4RDB is showing NOR flash size of 256MB in u-boot log. I'm running default U-boot version (U-Boot 2016.012.0+ga9b437f (May 15 2016 - 03:46:24 +0800)) that came with board. Here is snippet from boot log:

Board: T1042D4RDB
Board rev: 0x01 CPLD ver: 0x05, vBank: 0
SPI:   ready
DRAM:  Initializing....using SPD
Detected UDIMM 18ASF1G72AZ-2G3B1
6 GiB left unmapped
8 GiB (DDR4, 64-bit, CL=11, ECC on)
       DDR Chip-Select Interleaving Mode: CS0+CS1
Flash: 256 MiB
L2:    256 KiB enabled
Corenet Platform Cache: 256 KiB enabled
Using SERDES1 Protocol: 134 (0x86)
SEC0: RNG instantiated
NAND:  1024 MiB
MMC:   FSL_SDHC: 0
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734 Views
EmbEng
Contributor III

Thanks r8070z‌ for your response.

While much of confusion is cleared, I will write back here if any confusion arises again regarding this topic while modifying default DTS. Thanks.

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