Bus error generated by cpu

[ecil]

Hi,

iam currently working on P1013 processor in my board and for debugging laughterbach trace 32 tool is using.

After Initializing of MMU,LAWS(local access windows),CHIP select properties  and DRAM(DDR3) in my script through trace 32 tool iam able access the Internal memory and DDR memory.

when iam trying to access the eLBC memory it is showing as "bus error generated by CPU". we are unable to  access the eLBC memory.

OBSERVATION IN FPGA DEBUGGER:

When iam trying to  Access the eLBC memory, Jtag_hrst(COP_HRST) is generating from Trace 32 tool.

can you explain me what it could be the reason for above problem.

thank you... 

[yipingwang]

Please configure Local Bus memory controller BR0 AND OR0 registers according to your NOR flash. For details about these registers, please refer to p1022 reference manual.

if {$ROM_LOC == $GPCM_8BIT_BOOT_LOC} {
# boot from nor gpcm 8 bit boot location
# CS0 - NOR Flash
# BR0 base address at 0xF8000000, port size 8 bit, GPCM, DECC disabled
mem [CCSR 0x5000] = 0xF8000801
} else {
# boot from nor gpcm 16 bit boot location (default)
# CS0 - NOR Flash
# BR0 base address at 0xF8000000, port size 16 bit, GPCM, DECC disabled
mem [CCSR 0x5000] = 0xF8001001
}
# OR0 128MB flash size
mem [CCSR 0x5004] = 0xF8000FF7