B4860 PCIE Access from DSP Core

[nealebuckland]

I am attempting to access a PCIE endpoint connected to a B4860QDS from the a SC3900FP core.

The link is established correctly (as reported by u-boot) and I am able to perform memory writes using u-boot (via the 'mw' command). However, when I try to configure the SC3900FP to allow the same to occur, no activity occurs in my attached end point.

U-boot seems to configure the end point such that the BARs are 0xe1000000, 0xe2000000 and so on. There is a PCIE ATMU set to map 0xe0000000 to 0xc00000000 in the local address space. A LAW is configured for a base address of 0xc00000000 with the target set to PCIE.

If I write to an offset from 0xc00000000, I get a corresponding write in the endpoint at an offset from 0xe0000000. However, if I configure the same settings in the DSP, I don't get any activity in the end point at all.

Is there some additional configuration I need to do? Is the 0xc00000000 arbitrary, or does is have a specific meaning for the e6500 core (where u-boot is running).

[umairmalik]

Hi nealebuckland, 

We are in design phase of a project and have selected QorIQ B4860QDS for the application. It is required to connect FPGA core with processor through PCIe. FPGA will act as PCIe Endpoint (EP) while processor, running Linux supports PCIe RC (Root Complex) drivers only.
At this stage I need to confirm that this EP (FPGA) to RC (Processor) configuration is what is required to make communication between both and EP drivers at processor side are not required?

Secondly can you suggest me some practical guides/ read material to better acclimatize with B4860 and PCIe ?

[nealebuckland]

Hi Umair,

Yes, this is the same configuration we have, the B4860 is the RC and the FPGA is the EP. The B4860 can be solely a RC and no EP configuration is required there.

Not sure what to say about reading material – the B4860 reference manual is a bit lacking, and there don’t seem to be any demos.

I ended up trawling the internet.

Neale.

[umairmalik]

Thank you nealebuckland. 

How much effective Gbps were you able to achieve? Or what best throughout I should expect with 4 lanes and B4860 PCIe root complex?

[Pavel]

Check PCI inbound window under u-boot on your board. See the Section 23.1.2 of the B4860 Reference Manual. Draw attention on the Section 23.6.11 of the B4860 Reference Manual.

Have a great day,
Pavel Chubakov

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[nealebuckland]

I solved the problem myself - it turns out that the Memory Space Enable bit in the end point command register was not set, so the end point ignored the memory transactions. This bit is set when uboot is running, so must be cleared when the DSP starts up.