Hello,
I'm Trying to control output of HSD MC12XS6D1 using SPI. First of all I have sent two consecutive 16 bit frame of initialization1 were in one frame WD toggle bit was 1 and in another its 0, as mentioned in datasheet the WD bit should toggle in WD timeout. after that same for Initialization2, in response I'm getting Device status frame and in that FM,DSF,OVLF,TMF bits are set.
Thank you in advance and please guide me if I amdoing something wrong.
DSPI baudrate is 500kHz
Using continuous CS
Solved! Go to Solution.
Hello Pratik,
Let me copy here the answer I sent you internally yesterday and which helped to solve the issue.
Do you have a logic analyzer or an oscilloscope to see what is going on the bus and check the SPI timing?
I am not an expert on the MPC5775 MCU, I focus primarily on the analog ICs including the MC12XS6D1, but looking at the initialization you shared, it seems to me that the ClockPolariry should be set to Active low. As shown in Figure 9 of the datasheet, the MC12XS6D1 uses the “Mode 1” SPI protocol, which means that an inactive state of clock signal is low (CPOL = 0) and data are captured on the falling edge of clock signal and changed on the rising edge (CPHA = 1).
Best regards,
Tomas
Hello Pratik,
Let me copy here the answer I sent you internally yesterday and which helped to solve the issue.
Do you have a logic analyzer or an oscilloscope to see what is going on the bus and check the SPI timing?
I am not an expert on the MPC5775 MCU, I focus primarily on the analog ICs including the MC12XS6D1, but looking at the initialization you shared, it seems to me that the ClockPolariry should be set to Active low. As shown in Figure 9 of the datasheet, the MC12XS6D1 uses the “Mode 1” SPI protocol, which means that an inactive state of clock signal is low (CPOL = 0) and data are captured on the falling edge of clock signal and changed on the rising edge (CPHA = 1).
Best regards,
Tomas