eSDHC CMD protocol problem on QorIQ

[rvj]

Has anyone ever seen 6 bit messages on eSDHC CMD lines?

(FYI, the processor I am using is the P2020, but this seems to be a generic eSDHC problem).

The symptoms are that the processor will not recognise the SDHC card at all - not just a failure to mount, but wont recognise the card at all.

If you look at the command sequence being transmitted on the CMD line from the processor, instead of the usual 48 bit messages, it only transmits 6 bit messages.

The messages start with the correct bits, and end with the required stop bit, but all the other 42 bits are missing.

Something is telling the processor to behave this way - if anyone can help, I'd be very grateful.

[rvj]

After very lengthy investigations, it turns out that the processor is very sensitive to the impedance of the SDHC clock line. My design uses a 5 ohm series resistor to match the processor interface to the pcb 50 ohm trace, however, this is not sufficient. increasing this to 20 ohms (or 33 ohms as in the reference design) is all it needs the fix the problem.

I have several boards that have failed on this interface in different ways (sometimes no clock, sometimes electrically fine but fails to mount, etc) - in every case adding 20+ ohm resistor fixes the problem.

If anyone has trouble with this interface, this is one to watch out for.

Freescale's comment is that even though the clock is an output, the clock is fed back internally, hence it's sensitivity.

[hwrobel · Accepted solution]

You might want to double check how you connected the SDHC lines to the card cage, especially the clock line.

Do not put any pull ups or downs or other "paranoia" termination on the clock line. A 10-15 Ohm series resistor should be sufficient if you want to have a means of signal integrity control.

Then also ensure that any pull resistors on the other lines are according to the design checklist. If they are too strong, you run into trouble.

Don't terminate beyond what Freescale recommends or you could be subtly wrong.