Remapping u-boot in NOR-FLASH P3041

cancel
Showing results for 
Search instead for 
Did you mean: 

Remapping u-boot in NOR-FLASH P3041

Jump to solution
2,070 Views
rafaelcoelho
Contributor I

Hello all,

I am starting to use P3041 in a custom hardware (very similar with the P3041DS) and would like working with u-boot, but

I'm having a problem with NOR FLASH memory addressing. I'm using the Freescale SDK as reference and in this I have

following NOR_FLASH memory mapping.

ScreenHunter_56 Sep. 18 10.59.jpg

I my custom hardware I have the following NOR_FLASH memory mapping:

ScreenHunter_57 Sep. 19 17.39.jpg

The problem occur when I change the #define CONFIG_SYS_TEXT_BASE 0xefffffff to #define CONFIG_SYS_TEXT_BASE 0xe7b00000, thus

the image to u-boot after compilation has 133MB of size.

What are the addresses should I change to work with u-boot on this custom hardware?

Thanks very much.

Labels (1)
Tags (2)
0 Kudos
1 Solution
688 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Rafae,


The DDR SPD is on the target board, the parameters provided by DDR manufacturer in SPD could be used to configure DDR controller. Please refer to the following information in include/configs/corenet_ds.h.


#define CONFIG_DDR_SPD

#define CONFIG_FSL_DDR3

#define CONFIG_SYS_SPD_BUS_NUM  1

#define SPD_EEPROM_ADDRESS1    0x51

#define SPD_EEPROM_ADDRESS2    0x52

#define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1    /* for p3041/p5010 */

#define CONFIG_SYS_SDRAM_SIZE  4096    /* for fixed parameter use */

Is there SPD EEPROM on your target? If no, you could use fix or raw timing method to configure DDR controller, please refer to board/freescale/corenet_ds/ddr.c.

In addition, did you use CodeWarrior to debug u-boot to see where it is running?



Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
13 Replies
688 Views
scottwood
NXP Employee
NXP Employee

U-Boot goes at the end of flash.  You can't put it at arbitrary places such as 5MiB before the end.

The previous CONFIG_SYS_TEXT_BASE should have been something like 0xeff40000 or 0xeff8000, depending on U-Boot version (please specify such details when asking questions) -- not 0xefffffff.

Have you updated other symbols such as CONFIG_FLASH_BASE and CONFIG_FLASH_BASE_PHYS?

When you say that u-boot is "133MB", are you referring to u-boot.bin, or to the ELF "u-boot" file which has debug info, etc?

0 Kudos
688 Views
rafaelaugusto
Contributor I

Hello Scott,

U-Boot goes at the end of flash.  You can't put it at arbitrary places such as 5MiB before the end.

- The u-boot is at end of flash (0x2_E7B0_0000 - 0x2_E7FF_FFFF).


Sorry for my mistake about CONFIG_SYS_TEXT_BASE default value is 0xEFF80000. I am using u-boot source code in Freescale SDK V1.4.


Have you updated other symbols such as CONFIG_FLASH_BASE and CONFIG_FLASH_BASE_PHYS?

Not yet, because I don’t know what needs to be updated. Could you please tell me some reference to do this?


133MB is size of u-boot.bin file.


Thank you for your help.

0 Kudos
688 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Rafael,


If you use SDK 1.4 u-boot, it's better to allocate u-boot from 0x2_E7F80000 to 0x2_E7FFFFFF and define base address as the following.


#define CONFIG_SYS_TEXT_BASE    0xE7F80000


You also need to define reset vector address

#define CONFIG_RESET_VECTOR_ADDRESS    0xe7fffffc


According to your memory map, it seems that your are using 36 bit memory map, you need to use the definition in CONFIG_PHYS_64BIT.

#ifdef CONFIG_PHYS_64BIT

#define CONFIG_SYS_FLASH_BASE_PHYS      0x2e0000000ull

#else


If you allocate NOR Flash from 0x2_e8000000 to 0x2_efffffff, no need to modify much from the default.


Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

688 Views
amarnathmb
Contributor III

Hi Yiping,

I also face the same issue. I'm trying to relocate default NOR Flash mapping in T1040D4RDB Uboot from 0xe8000000 to 0xF0000000. So as per the suggestion given in above reply I modified CONFIG_SYS_FLASH_BASE as 0xF0000000, CONFIG_SYS_FLASH_BASE_PHYS as 0xFF0000000, CONFIG_SYS_TEXT_BASE as 0xF7F40000 and CONFIG_RESET_VECTOR_ADDRESS as 0xF7FFFFC. 

I'm using uboot 2019 from DENX git repo.

I have also added TLB and LAW entry for NOR flash.

TLB : VIRT=0xF0000000, PHYS=0xFF000000, SIZE=256MB

LAW: ADDR=0xFF000000, SIZE=256MB

After i flash and try to boot the uboot nothing is printed on the console. 

Is there anything else I need to configure? 

Thanks in advance for all your help.

0 Kudos
688 Views
rafaelcoelho
Contributor I

Hello Yiping,

I applied your suggestion and now the u-boot.bin size is 512KB at (0x2_E7F80000 to 0x2_E7FFFFFF).  But, still not working and I don't know what happens. Using debugging tool and disassemble the first instruction I have:

PC: 0xFFFFFFFC

$0FFFFFFFC   : 0x4BFFF004 :ppc b              0xfffff000

at address 0xfffff000, I have the following disassembled code:

$0FFFFF000   li                   R1,0x200            

$0FFFFF004   mtmsr          R1                  

$0FFFFF008   mfspr           R3,0x3ff            

$0FFFFF00C   clrlwi           R3,R3,0x18          

$0FFFFF010   li                  R4,0x10             

$0FFFFF014   cmpw          R3,R4               

$0FFFFF018   beq              0xfffff030          

$0FFFFF01C   li                 R4,0x11             

$0FFFFF020   cmpw          R3,R4               

$0FFFFF024   beq             0xfffff030          

$0FFFFF028   li                 R27,0x0             

$0FFFFF02C   b                0xfffff050          

$0FFFFF030   li                 R27,0x1             

$0FFFFF034   sync

I appreciate some suggestions.

Thank you for your help.

0 Kudos
688 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Rafael,

Did you import u-boot elf file(u-boot) into your debug tool? u-boot disassembled code should be like the following.  Would you please provide your u-boot.map file  in the build folder P3041DS?

fffff000:  li r0,2

fffff004:  mtspr spr1010,r0

fffff008:  mtspr spr1011,r0

fffff00c:  mfspr rsp,spr304

fffff010:  mtspr spr304,rsp

fffff014:  li r2,32

fffff018:  mtspr spr606,r2

fffff01c:  lis r2,0

fffff020:  ori r2,r2,0x0102

fffff024:  mtspr spr1011,r2

fffff028:  mfspr r3,spr1011

fffff02c:  and. rsp,r3,r2

fffff030:  bne 0xFFFFF028 (0xfffff028) ; 0xFFFFF028

fffff034:  lis r3,1

fffff038:  ori r3,r3,0x0001

fffff03c:  mtspr spr1011,r3

fffff040:  isync


Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
688 Views
rafaelcoelho
Contributor I

Hello Yiping

I have not imported the u-boot file in debug tool, I recorded the file (u-boot.bin) at NOR_FLASH

and I did dump of memory. Attached you have the u-boot.map

Thank you for your help.

0 Kudos
688 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Rafael,


The generated u-boot image should be normal, I use objdump to dump the elf file and get the same disassembled code with you at boot page section.


For LAW and MMU TLB configuration please refer to files law.c and tlb.c in board/freescale/common/p_corenet/, the configuration should be related with CONFIG_SYS_FLASH_BASE_PHYS and CONFIG_SYS_FLASH_BASE in the header file. For DDR, the default configuration is using SPD.


I suggest you use CodeWarrior to debug u-boot to check where it is stuck, please refer to the document CodeWarrior U-Boot Debugging, for detailed information, please refer to the section "Debug u-boot using NOR Flash" in CodeWarrior document CW_PA_v10.4.0\PA\Help\PDF\Targeting_PA_Processors.pdf.




Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
688 Views
rafaelcoelho
Contributor I

Hello Yiping,

What is the memory used in P3041DS board that stores the setting of SPD?

Could you explain me how it is generated configuring SPD?

The u-boot SDK v1.4 does not contain instructions for fixed configurations, the file

p3041ds_ddr.c has the following code:

fixed_ddr_parm_t fixed_ddr_parm_0[] = {

      {0, 0, NULL}

   };

  

This mean, that is not implemented! I am right?

Thanks.

0 Kudos
689 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Rafae,


The DDR SPD is on the target board, the parameters provided by DDR manufacturer in SPD could be used to configure DDR controller. Please refer to the following information in include/configs/corenet_ds.h.


#define CONFIG_DDR_SPD

#define CONFIG_FSL_DDR3

#define CONFIG_SYS_SPD_BUS_NUM  1

#define SPD_EEPROM_ADDRESS1    0x51

#define SPD_EEPROM_ADDRESS2    0x52

#define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1    /* for p3041/p5010 */

#define CONFIG_SYS_SDRAM_SIZE  4096    /* for fixed parameter use */

Is there SPD EEPROM on your target? If no, you could use fix or raw timing method to configure DDR controller, please refer to board/freescale/corenet_ds/ddr.c.

In addition, did you use CodeWarrior to debug u-boot to see where it is running?



Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
688 Views
rafaelcoelho
Contributor I

Hello Yiping,

I don't have EEPROM SPD. I configured fixed method to DDR controller in board/freescale/corenet_ds/ddr.c :smileyhappy:. But now I have some problems, because in my board I don't have ngPixis and u-boot uses it, to get clock configuration. So during initialization the hang() function is called and so all is interrupted :smileyangry:.

0 Kudos
688 Views
adeel
Contributor III

Hi,

0xFFFFF000 is the boot page section where your start_e500 resides. Your u-boot is running and now you need to setup TLB, LAWs and setup DRAM so that u-boot can relocate itself to DRAM.

Best Regards,

Adeel

0 Kudos
688 Views
rafaelcoelho
Contributor I

Hi,

How can I know if the u-boot is working? Because, I have not any print (serial console), Do you know if there are others status that can I verify?

How do I setting TLB, LAWS and DRAM? This is already done by u-boot or not?

Thank you.

0 Kudos