In section 13.4.2.3.4 of QorIQ P2040 Reference Manual Rev 4, it specifies that local bus signal LOE_B asserts and negates on the rising edge of the bus clock, but in the read figures (e.g. Figure 13-14 or 13-15) the signal appears to transition on the fal

[gradymuldrow]

In section 13.4.2.3.4 of QorIQ P2040 Reference Manual Rev 4, it specifies that local bus signal LOE_B asserts and negates on the rising edge of the bus clock, but in the read figures (e.g. Figure 13-14 or 13-15) the signal appears to transition on the falling edge of LCLK.  Which edge does it transition on?  Thanks, Grady

[ufedor]

P2040 only supports the PLL bypass mode. 

What is stated in the datasheet is correct. LOE is driven at the falling edge.

2.14.2.1 Local Bus AC Timing Specification All output signal timings are relative to the falling edge of any LCLKs. The external circuit must use the rising edge of the LCLKs to latch the data.

All input timings except LGTA/LUPWAIT/LFRB are relative to the rising edge of LCLKs. LGTA/LUPWAIT/LFRB are relative to the falling edge of LCLKs.