Dear Sir / Madam,
I have a few questions, and I hope some which can help me interpret the I2C bus specification.
The I2c specification shows a SDA/SCL slope control – rising /falling time for 400KHz speed (Fast Mode) as 20nS + Cb*0.1 [ where Cb is bus capacitance] , which is shown as attachment(red square).
I would like to know:
Sincerely,
Thank you,
Jerry.chien
Hi David,
I have the same question for tr/tf. Is it must to meet the min time 20ns+0.1*Cb?
What happen if tr/tf is smaller than 20ns?
Hello Jerry,
I hope all is great with you.
First, tr is defined as the amount of time taken by the rising edge to reach 70% amplitude from 30% amplitude for either SDA and SCL, while tf is defined as the amount of time taken by the falling edge to reach 30% amplitude from an amplitude of 70%.
Note that the rise time is defined by the external parameters: pullup resistor and capacitive load values. Fall time is determined by the output driving capabilities, pullup resistor and capacitive load values.
Usually, the I2C output specifications can be obtained from the IBIS model.
Let’s assume that this model shows that the I2C output impedance is about 40 Ohm. For maximum specified 400pf load, so the fall time is R*C ~ 20ns. This time complies with the I2C-bus specification.
The rise time is defined by the pullup resistor as below. The minimum pullup value is determined by the output capabilities of all devices on I2C bus.
R*400pF<1000ns (maximum value is specified by the I2C standard).
So, R must be less than 2.5K to support maximum load 400pF.
I hope this information helps.
Regards,
David