It is quite well described in following appnote:
http://cache.freescale.com/files/32bit/doc/app_note/AN2865.pdf
Figure 9 describes SW vector more, Figure 12 describes HW vector mode.
Most of the customer use SW vector mode. It is like “default” mode. HW vector mode you would use in case you would need extremely fast ISR response for some sources - the disadvantage would be this approach takes more memory. If you currently don’t have specific requirements, use software vector mode.
First let me clarify terminology regarding exceptions and interrupts:
Considering SW mode, all sources routed from interrupt controller into IVOR4 can be told as “interrupt” (RM names it as external interrupt), all other IVORs may be considered as “exception” (RM says interrupt). Little bit confusing but common terminology from outside world is exception and interrupt.
Some notes to HW vector mode - As AN2865 explains it well I would only added some info how to deal with exceptions and interrupts handlers in one project.
Exception branch table must be located above or behind interrupt branch table in dependency on used core as follows:
e200z1, z3, z4, z6, z7:
ISR address = IVPR + offset given by INTVEC
ESR address = IVPR + offset given by particular IVOR register (IVOR4 inactive)
Thus it means you must set IVORx register to have final address behind interrupt branch table.
e200z0 (all offset are fixed):
ESR address = IVPR + fixed offset starting from 0x0000
ISR address = IVPR + fixed offset starting from 0x0800
Thus in this case exception table is before interrupt table.
