Spurious DMA interrupts related to SPI-Rx

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Spurious DMA interrupts related to SPI-Rx

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Contributor III

Hi,

We are using MPC5746C controller and implemented SPI in full duplex mode.

2 DMA channels are configured for both SPI-Tx & SPI-Rx.

Also, interrupts are enabled which will be triggered upon the completion of both SPI-Tx DMA & SPI-Rx DMA.

In Interrupt routine, Destination address is updated for both the DMA channels (ping-pong buffer implementation).

With the above mentioned implementation, we are observing spurious SPI-Rx DMA interrupts.

Major Loop count is '1' & minor loop count is '64'.

Could you pl let us know the causes for this spurious interrupts ?

Regards,

Satya Sudhir

7 Replies

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

it sounds like some kind of coherency issue. Is DREQ bit set in your descriptors? When you reconfigure the descriptors in interrupt handler, are the DMA channels disabled at this moment?

Regards,

Lukas

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Contributor III

Hi lukaszadrapa, sumeetkumarsahu12@gmail.com

Thanks for your reply. 

DREQ bit is set in our code and hence, DMA requests are disabled upon the completion of major loop transfer.

Could you please let us know the way of altering the priority b/w CPU (Z4 core) and DMA masters as we are suspecting the problem would be due to contention & hence, wanted to try by configuring XBAR (AXBS_0) registers to give highest priority to DMA which may resolve spurious interrupts issue.

Please point us to the right set of registers for changing the priority.

Regards,

Satya Sudhir

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi Satya,

as a first step, I would try to enabled priority elevation for corresponding DMA descriptors, so the core performance is not affected by global priority settings. Here is an example:

/* Enable priority elevation for DMA (master port 6) for slave ports 3 - 6 (PBRIDGE_A, PBRIDGE_B, PRAM_0, PRAM_1) */
for(i=3; i<=6; i++)
   AXBS_0.PORT[i].CRS.B.HPE6 = 1;

And then for corresponding DMA descriptors:

/* Enable eDMA master high-priority elevation (HPE) mode. No eDMA engine stalls. */
DMA.TCD[CHANNEL].CSR.B.BWC = 1;

Regards,

Lukas

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Contributor III

Hi Lukas,

Thanks & appreciate your timely response.

I already went through AXBS_0 registers for configuring the priority of DMA but it is for below slave ports only

PBRIDGE_A,

PBRIDGE_B,

PRAM_0,

PRAM_1,

PFLASH

In our case, Source address for DMA associated with SPI-Tx is a buffer which resides in SRAM (not related to any of the above mentioned slave ports).

So, I am not clear about the slave port as it is not mentioned in the block diagram of Cross bar switch in MPC5746C CRM.

Please suggest.

Regards,

Satya Sudhir

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

this snapshot from the reference manual should explain it:

pastedImage_1.png

Regards,

Lukas

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246 Views
ssure
Contributor III

Hi davidtosenovjan

Please look into my query and respond. it will be helpful.

Regards.

Satya Sudhir

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246 Views
ssure
Contributor III

Adding to the above info,

When we disabled DMA channel for SPI-Tx, we didn't observe spurious interrupts issue with DMA for SPI-Rx.

Regards,

Satya Sudhir

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