MPU PID MPC5777C

[Othmane1]

Hi,

can anyone tell me how the MPU knows which PID every task has? should i set the PID somehow of each task in some special register? because the only thing i found in the reference manual of the MPC5777C is this :

where does the pid_hit get the current pid? 

[davidtosenovjan]

It is given by setting of PID0 core register as on screenshots below:

[Othmane1]

so if i want to have two tasks each with it's own PID i should so something like this:

void vTaskLed(void *pvParameters)
{
struct TaskLed *apCtx = (struct TaskLed *) pvParameters;
static uint32_t test_read;

for ( ; ; )
{
__asm (
"e_li %r3,0xffff8001\n" // Load the value 0x12345678 into r0
"mtspr 48,%r3\n" // Write the value in r0 to the TBL SPR (SPR number 48)
);
*(uint32_t*)0x4003F000u = 0x1;

gpio_write(apCtx->led, 1);

MSLEEP(TASK_DELAY_1000MS);

gpio_write(apCtx->led, 0);

MSLEEP(TASK_DELAY_1000MS);
}
}

void vTaskLed1(void *pvParameters)
{
struct TaskLed1 *apCtx = (struct TaskLed1 *) pvParameters;
static uint32_t test_read;

for ( ; ; )
{
__asm (
"e_li %r3,0xffff8002\n" // Load the value 0x12345678 into r0
"mtspr 48,%r3\n" // Write the value in r0 to the TBL SPR (SPR number 48)
);
//*(uint32_t*)0x4003F000u = 0x2;

gpio_write(apCtx->led, 1);

MSLEEP(TASK_DELAY_500MS);

gpio_write(apCtx->led, 0);

MSLEEP(TASK_DELAY_500MS);
}
}

[davidtosenovjan]

Yes, in principle it should be like that.

Consider there are also synchronization requirements for accesses to PID registers.

[Othmane1]

can you elaborate a little bit on these synchronization requirements?

[davidtosenovjan]

In general way –

Any instruction that alters the context in which data addresses or instruction addresses are interpreted, or in which instructions are executed, is called a context-altering instruction. A Context Synchronizing Instruction ensures that all changes due to context altering instructions have taken effect.

It is stated either in core RM or EREF RM as well as synchronization requirements for SPRs. EREF RM, section 5.5.4 Synchronization.

Write to PID0 register (spr 48) needs to be followed and predecessed by 'isync', then the solution is bulletproof.