ERR007001: External TA and TEA do not operate properly when internal master does burst aborts to EBI

[puneeth_bheemar]

Hi Team,

We are considering the utilization of an external TA signal for the EBI interface in our design. While reviewing the reference manual and errata documents, we've identified potential issues related to employing external TA/TEA signals for the EBI interface, specifically in burst mode operations.

Nonetheless, it's crucial to clarify that our intention is to utilize the EBI interface exclusively in Single Beat Transfer mode, with no plans to use Burst Transfer mode. Therefore, we kindly request confirmation regarding the using the TA pin of the EBI interface for Single Beat Transfer operations.

Thank you,

Puneeth KB

[davidtosenovjan · Accepted solution]

A workaround I am describing below is suitable as well:

If you have used external TA for certain area of EBI space then another workaround for the issue is to avoid bursting from internal masters:

CPU - core access to this area needs to be set as cache inhibited, thus there will be no bursting due to cache line filling
FEC - disable bursts to EBI by PCM_FBOMCR register
eDMA - do not use TCD’s SSIZE/DSIZE = 0b101 i.e. 32-byte bursts

If there are no bursts there are no burst aborts and ERR007001 does not happen.

To answer your question - errata wording speaks about burst transfers over internal bus. It is not related to burst configuration of EBI.