MPC5748G EEE_ERR_IVOR_EXCEPTION

[skseofh]

Hi, I'm using MPC5748G EEE module.

In SDK EEE example, there are codes that invalidate flash controller cache.

If I not using these codes, is there any problem?

From what I've tested, it seems to trigger IVOR interrupt If I don't use the above codes.

Do I always have to invalidate the flash controller cache to use EEE?

And could you give me more details about IVOR interrupt?

[lukaszadrapa · Accepted solution]

Hi,
the buffer is invalidated automatically by interlock write. However, as mentioned in the reference manual (https://www.nxp.com/webapp/Download?colCode=MPC5748GRM "an interlock write invalidates only the buffers associated with the system bus port on which the interlock write was issued". There are three ports on flash in case of MPC5748G. That means: if EEE code is executed on Z4A core, only buffer on PFLASH_1 port (this one is used for Z4A data bus) will be automatically invalidated. See Table 16-1 in the RM.
So, there should be no problem if you read EEE data only by Z4A core. If it is read also by other cores, it may lead to coherency issues.
It's not clear to me why IVOR1 is triggered. You can take a look at the core reference manual for more details:
https://www.nxp.com/webapp/Download?colCode=E200Z4RM&location=null
See Table 5-13. This can help to find more details about the source of problem. Core register MCSRR0 contains address of instruction which caused the error and MCSR contains the reason of this error.
Regards,
Lukas

[skseofh]

Hi, thanks for the reply.

As you said, there are three ports on flash(MPC5748G), and each port has a read buffer.

1) Is it right that each core only can access each buffer associated with the system bus port?

   - for example, Z4a I bus only can access PFLASH_0 buffer.

                          Z4a D bus only can access PFLASH_1 buffer.

2) In case of using EEE module only by Z2 core, is it right that I don't have to invalidate other flash controller cache(p0, p1)? (Because Z2 core only uses PFLASH_2.)

[lukaszadrapa]

1. Yes, that's correct.

2. If EEE runs exclusively on Z2 core only, you do not need to invalidate p0 and p1.

Regards,

Lukas

[petervlna]

Hello,

regarding IVOR1:

Best regards,

Peter

[skseofh]

Thanks for reply!

I have one more question.

Do I HAVE TO invalidate flash controller cache to use EEE?

If I have to, why?