MPC5746B AIPS Peripheral Assignment

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

MPC5746B AIPS Peripheral Assignment

1,533 Views
cholland
Contributor V

I trying to figure out AIPS / PBridge.

1. I don't understand the difference between the two types of Register sets?

   A. Peripheral Access Control Register

   B. Off-Platform Peripheral Access Control Register

2. In the reference manual, it reads "The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip." What does it mean by most?

I would like to know what the peripheral control registers were actually mapped to which peripheral.

Somebody else had the question, but it's for a different processor

Does anybody know which peripherals are assigned to the AIPSTZx_OPACRy fields? 

3. I'm noticing a problem with a specific register. PACRE

reg_value = AIPS_A.PACR[0].R;  /* Works fine */

reg_value= AIPS_A.PACR[1].R;  /* Works fine */

reg_value= AIPS_A.PACR[2].R;  /* Works fine */

reg_value= AIPS_A.PACR[3].R;  /* Works fine */

reg_value = AIPS_A.PACR[4].R;  /* IOVR */

reg_value= AIPS_A.PACR[5].R;  /* Works fine */

reg_value = AIPS_A.PACR[6].R;  /* Works fine */

reg_value = AIPS_A.PACR[7].R;  /* Works fine */

All OPACR[] registers work fine.

"If a peripheral is absent, the corresponding PACR field is not implemented. Reads or
writes to the location of an unimplemented PACR register (because all eight of its
peripherals are absent) should be avoided to prevent undesired behavior."

I guess it must be absent?

Thank you,

Labels (1)
2 Replies

1,163 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi,

1) "Platform" is a such vague term and its meaning can be various

In this context it is set of modules close to the core or system modules, typically the same or similar set is used with other MCU derivatives and these ones are called "On-platform" peripherals.

Here these are following ones:
XBAR, PBRIDGEs, SMPU, PCM, RAM a FLASH controllers, INTC, eDMA, SWT, STM and Semaphores

The rest are just off-platfrom peripherals.

2) SRAM and FLASH are basically peripherals as well and these are not accesses over PBRIDGE - explaining what "most" stands for.

The list of peripheralas and its PACR/OPACR assignment you may see in the RM, section 3.6

pastedImage_2.png

3) According to sentence you have mentioned and Table 3-5 implicates PACR32-39 fields does not exist and PACRE register should not be accessed at all.

pastedImage_5.png

pastedImage_3.png

1,164 Views
cholland
Contributor V

I came back after a spell.

I had to updated the post, because the terminology is a bit confusing.

I would expect the register to return 0x0, instead of an IOVR. It does that for other unused PACRs.

"...Reads or writes to the location of an unimplemented PACR register (because all eight of its
peripherals are absent) should be avoided to prevent undesired behavior." Hence the IOVR.

pastedImage_1.png

0 Kudos
Reply