MPC5744P ADC Self test issue

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MPC5744P ADC Self test issue

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Contributor II

I have an issue regarding the MPC5744P ADC self test. I am reading the bandgap voltage from the channel 10 of all the ADCs( i.e ADC0, ADC1, ADC2, ADC3 ) and I have followed the steps given in the ADC self test application note. ( Link given below ): https://www.nxp.com/docs/en/application-note/AN5015.pdf 

initially I have tested only step 0 ( ALG 0 ), i.e to measure the band gap voltage which is obtained in the STDR1[TC_DATA] and valid bit STDR1[VALID] should be set, when the MCR[NSTART] is done.

But in my case, the STDR1[TC_DATA] is updated correctly as 1.19V, but the valid bit is set initially and getting cleared when I am waiting for end of conversion ( EOC ) flag to get updated. But STDR1[TC_DATA] is still present even after the valid bit is cleared. I have attached the screenshots of the register values obtained during the test.

  • Screenshot showing the value of STDR1 register value after MCR[NSTART].( right side in yellow colour ).

pastedImage_1.png

  • Screenshot showing the STDR1 register value in the next step after the while loop is executed. That is to wait till end of coversion flag is updated. In this case the valid bit is cleared and only the TC_DATA which is the band gap voltage is present.

pastedImage_2.png

Code part is followed same as given in the application note mentioned above. Can anyone please let me know, if any other changes in the initialization or configuration is required to solve this issue.

Thank you in advance.

7 Replies

14 Views
NXP Employee
NXP Employee

Hello,

Hmm, I am not sure what is the behavior is you do not do ALG S at once.

Its been some time since I have done the tests.

step 0 ( ALG 0 ),

What algorithm are you referring? S?

Try execute S test in scan mode to see the results,

regards,

Peter

14 Views
Contributor II

Hello Peter, Thanks for your reply.

Yes. I am testing ALG S ( Step 0 ), which is to measure the band gap voltage.

I am not sure if it works for scan mode, but I need one shot mode also for my application.

In addition I tested the Step 1 also, which is to measure the analog supply voltage where I got the voltage value correctly within the thresholds set, but the valid bit was still not set in this case also. I followed the steps given below in the screenshots.

pastedImage_1.png

pastedImage_2.png

Please let me know if you find any other way through. Thank you

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14 Views
NXP Employee
NXP Employee

Hi,

OK, I see this application note is rather simple then explaining the ADC self tests in details.

Try to read mine one I have published long time ago in ST:

https://www.st.com/content/ccc/resource/technical/document/application_note/cc/7d/12/60/aa/a8/46/53/... 

Don't worry the micro is exactly the same.(it is from joint venture times between Freescale and ST)

I explain there why you should not execute S alg in single shot mode.

But from my experience, I had no issue executing the S alg steps sequential in evaluation board. But in real project I would not do that.

My code is embedded in the application note.

If you like you can share your code where you demonstrate the issues and I can test it here.

regards,

Peter

14 Views
Contributor II

Hey Peter,

Thanks for the reply. I had referred the ST application note published by you and agree that in one shot mode, the incorrect measurement of the supply voltage may be masked if the measurement is delayed from the S0 measurement as S1 is dependent on S0.

But I did not get why NXP has provided the 'one shot mode' ( with procedure and code details ) in self test if it is not reliable ? Is this mode used in particular applications only?

Anyways, I perform the self test in scan mode ( referring both applications notes ) and get back if there are any issues. Thank you for the support.

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NXP Employee
NXP Employee

Hi,

But I did not get why NXP has provided the 'one shot mode' ( with procedure and code details ) in self test if it is notreliable ? Is this mode used in particular applications only?

Its hard to tell, I have reported this years ago :smileyhappy: but seems no action was taken.

regards,

Peter

14 Views
Contributor II

Hello Peter,

Thanks for the reply.

I performed the ADC self test in scan mode. I came across one issue. The ADC reference voltage is always measured as ( 0xFFd - 0xFFF , approx 4091 - 4096 mV ). I have made the ADC reference voltage to dip below 4096 by loading the ADC supply, that is around 3850 mV and the lower threshold is set to 4089( 0xFF9 ) as given in the application note.

I have checked the ADC reference voltage both in scan and one shot mode.

In scan mode, the ERR_S2 bit of STSR1 register is not set even though there is dip in the ADC reference voltage.

In one shot mode, I have measured the reference voltage ( from TCDATA of ADC_STDR1 register ) after performing the step 2 of S algorithm and found that this voltage value is still around  4096 mV and not changed and the ERR_S2 bit of STSR1 register is also not set. But we checked the reference voltage by probing on the board which was around 3850 mV.

The normal ADC channels are read using the ADC reference voltage, but in order to measure the ADC reference voltage , what value is taken as reference voltage?

Thank you.

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14 Views
NXP Employee
NXP Employee

Hello,

The behavioral which you are seeing is correct because during this test is used the Vref also as a reference voltage so when the Vref is change it always give full output code. This test is checking if there is some issue in the circuit. See the description of the ERR_S2 bit in the ADC_STSR1 register (ERROR occurred on the sampled signal).

regards,

Peter

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