MPC-5125 ECC Status Byte Location

[Tim562]

Hi All,

        Does anyone know where the ECC status byte for a NAND flash read operation can be found after the read op is complete? Manual allows spec of a 9 bit offset "ECC_SRAM_ADDR" and an enable bit "ECC_SRAM_REQ" located in the FLASH_CONFIG register. Manual says that the ECC status byte (if enabled) will be written to the sram buffer used for the page read at a location defined by ECC_SRAM_ADDR + 0x07. Well, with only 9 bits, I can only locate the status word a max of 512 bytes (+ 0x07) from the start of the buffer. Buffers are 2304 bytes in size and my page reads are 2048 byte pages so I need to spec the status word be written at some point beyond the end of the 2048 bytes of read page data.

        From looking at the MQX code it appears that maybe the ECC_SRAM_ADDR spec's an offset beyond the end of the read page size. So a value of 0 with a 2048 page read means that the status word should end up in the sram buffer at index 2048 (+ 0x07), right? Well, doesn't seem to be there. Further looking at MQX code it appears that when the high level MQX read() command is used, MQX looks for the ECC status at an index defined by the page read size, a constant defined as 0x0C? What the heck? Anybody used the Nand Flash Controller to read a Nand Flash device and retrieved the ECC Status byte? Where did you look to get the status byte? Processor manual I'm using is revision 2 11/2009. Thanks!

Best,

Tim

[Pavel]

Location of the ECC status byte is ECC_SRAM_ADDR + 0x07.

See attached file. It is simple program example for the MPC5125 NAND Flash controller.

Find the fsl_nfc_check_ecc_status finction in the fsl_nfc.c file.

Have a great day,
Pavel Chubakov

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