Well, this is kind of weakness of the documentation. Sometimes names of internal signals soaked to the reference manual and it's nor clearly explained.
In this case, p_dmem_rstcfg are hardcoded signals. The result is that reset value of DMEMCTL0 register is 0x0000041B.
p_hwchkbit[7:0] is then internal bus for e2eECC:
Maybe this draft of application note and examples from my colleague could help:
Regards,
Lukas
Hi Jamber,
these are internal input signals of the core which are used to provide configuration information for operation out of reset. In this case, these signals are 0b0000. As defined in the RM, reset value is:
Reset - 0x5 || p_e2e_rstcfg[0:3];
That means the reset value is 0x5.
Regards,
Lukas
Well, this is kind of weakness of the documentation. Sometimes names of internal signals soaked to the reference manual and it's nor clearly explained.
In this case, p_dmem_rstcfg are hardcoded signals. The result is that reset value of DMEMCTL0 register is 0x0000041B.
p_hwchkbit[7:0] is then internal bus for e2eECC:
Maybe this draft of application note and examples from my colleague could help:
Regards,
Lukas