Hello,
We are injecting ECC errors in Flash according to example "MPC5744P_1b+2b_FLASH_ECC_error_by_UTEST_area_read-v0_0-GHS614".
For FCCU NCF[22] "Flash uncorrectable ECC error" we have configured reaction to 'long reset. For FCCU NCF[21] "Flash correctable ECC error" we have configured reaction to 'no reaction'. But, we can although observe that there is a MCU reset performed when triggering the "Flash correctable ECC error". What can be the cuse of this reset?
The last comment in example function Inject_1bit_FLASH_ECC_error_by_UTEST_read() is
// ECC is checked and non-correctable error found
But, it should be
// ECC is checked and correctable error found
??
Best Regards,
Peder Rogö
Hi,
thanks for your quick response.
There are two reasons set in MC_RGM_DES:
01: A FCCU failure to react reset event has occurred
01: A power-on event has occurred
No reason is set in MC_RGM_FES.
FCCU NCFE21 is disabled, i.e. FCCU_NCF_E0 is set to FFFFFBFF.
Thus, no reset should expected at when running Inject_1bit_FLASH_ECC_error_by_UTEST_read()?
BR,
Peder
This destructive reset source comes from FOSU. On this device it works the way that whichever NCF fault has enabled any FCCU reaction, FOSU is enabled. And in case no reaction happens on FCCU fault (even in case it is other source than the one having enabled its reaction) until FOSU timeout, destructive reset is triggered.
In your case the solution is to enable interrupt reaction for NCF[22] and clear this fault in FCCU ISR when happens (as this single error is automatically correct, no other reaction is needed).
Hi, thanks for your report, these are just typos in C comments.
To your question -
Have you checked MC_RGM_DES and MC_RGM_FES to investigate actual reset reason?