After enabling instruction cache and data cache, Ethernet and SDIO work abnormally

[zyz]

Hello everyone，I am using MPC5748G, and I have encountered some problems recently. When I enable the instruction cache and data cache, I occasionally fail to mount the SD card, the f_mount function return

FR_NO_FILESYSTEM, and the Ethernet is abnormal, and the ping fails. Regarding the instruction cache and data cache , Is there anything to pay attention to?

[lukaszadrapa]

Hi,

it's important to remember that there's no hardware cache coherency unit between the bus masters. Data cache and instruction cache is a feature of core only. Other bus masters (other cores, ENET, DMA...) don't know if a cache is used on a core.

So, following situation can happen: a core reads (and loads to cache at the same time) some data from RAM. If another bus master changes the data in RAM now, the core is not informed about that. If the core reads the data again, it will read old/wrong data from cache because that cache line is still marked as valid.

Solution: If the core knows that another bus masters can change those data, it's necessary to invalidate the cache before such read. It is possible to invalidate only certain cache lines or whole cache. Another option is to configure such RAM area as cache inhibited - this is better solution, I think. SMPU module can be used for this configuration.

Regards,

Lukas

[zyz]

Thank you for your reply, but how do I know which RAM areas need to be configured as cache inhibited? As you said, if another bus master now changes the data in the RAM, it will not notify the kernel, that is, all rams are This may happen, does that mean that all RAM needs to be configured as cache inhibited?