According Operation of EBI BUS - MPC5674 MCU

[juntae_kim]

Dear sir of madam.

Hello.

I'm Juntae Kim in Korea of republic.

I've used the MPC5674 MCU.

I wondering about the operation of EBI BUS's read cycle.

When I read the data using the EBI BUS, D_TS signal is asserted.

As I know, EBI BUS ready to valid data, the D_TA signal is asserted.

At this point, I have a question.

D_TS signal did not asserted in the master, but does it cause a problem when the D_TA signal is generated in the slave?

Also, If D_TA signal is continuously generated without D_TS signal assertion, does it cause a problem?

Please let me know.

best regards.

Juntae Kim.

[davidtosenovjan]

Hi, I am not completely sure if I understand the question but I will try.

There are two modes, either internally or externally terminated (according EBI_BRx[SETA] for CS access, or always externally terminated for non-CS access).

Whether TA is drive by a master or a slave, it is given by using of internally or externally terminated configuration. It cannot work simultaneously, you cannot have configured internally terminated and terminate externally.

I could recommend to see following:

https://community.nxp.com/docs/DOC-101725 

[juntae_kim]

Hi david.

Thank you for your answer.

I have additional question

- My system architecture

  : MPC5674 and FPGA are connected using the EBI.

  : MPC5674's EBI mode is externally terminated mode.

  : When MPC5674 reads the data from FPGA, MPC5674 asserts TS signal.

  : When FPGA finish the process sending data, FPGA asserts TA signal.

- Wondering point

  : My FPGA often sends a TA signal when the TS signal is not input from the MPC5674.

  : I don't think it will be a problem, what is your opinion?

[davidtosenovjan]

So you are using externally terminated mode. Are you asking whether asserting of TA without previous assertion of TS will cause a problem? It is some false acknowledge or how you mean it? Why FPGA asserts TA wihout a reason?

[juntae_kim]

The reason for asserting TA without assertion of TS is my programming mistakes.

However, My program is running without any problems now.

A large modification is required to change.

So If it does not cause any problems, I want to use this program without modification.

[davidtosenovjan]

In my opinion it could not cause any issue with that. I haven't found anything what would speak against it. If cycle does not start, it should not be an issue to terminate it. That's however only my opinion.

[davidtosenovjan]

Is FPGA the only device connected to EBI or there is other devices connected there?

[juntae_kim]

also, SSRAM connected to EBI.