How to setup SWO, ETM, ETB trace debugging

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How to setup SWO, ETM, ETB trace debugging

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isaotakashima
Contributor IV

Our customer interested MCUxresso IDE, because KDS (Kinetis Design Studio) does not support trace debugging feature.

According to the MCUXpresso fact sheet, MCUxpresso does support the following trace feature.

- Instruction Trace

- SWO Trace/Profiling

They have the J-Link, then they believe that they can debug using SWO Trace/Profiling.

Are they correct?

How about Instruction Trace? Can they debug use Instruction Trace?

They understand that they should purchase J-Trace to debug with ETM.

They would like to know which item is different from free edition for Professional edition.

Please reply as soon as possible.

Best regards,

Takashima

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lpcxpresso_supp
NXP Employee
NXP Employee

MCUXpresso IDE's built in support for SWO trace and instruction trace is for use with LinkServer debugger connections (not JLink I'm afraid).

For SWO Trace you need a LPC-Link2 debug probe (with the CMSIS-DAP firmware supplied as part of MCUXpresso IDE). This does require a Cortex-M3/M4 based part with the SWO pin connected to the SWD connector on the board.

For instruction trace, you can use any LinkServer connection (including many other CMSIS-DAP probes, including OpenSDA circuits). This requires an M3/M4 based part with an ETB incorporated, or M0+ based part with MTB.

For more details, please consult the documentation provided with MCUXpresso IDE or downloadable from the Documentation tab of http://www.nxp.com/mcuxpresso/ide 

Regards,

MCUXpresso IDE Support

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danielholala
Senior Contributor II

lpcxpresso_support wrote:

... 

For instruction trace, you can use any LinkServer connection (including many other CMSIS-DAP probes, including OpenSDA circuits). This requires an M3/M4 based part with an ETB incorporated, or M0+ based part with MTB.

 ...

I digged out this old posting while looking for information about ETM. For the sake of clarity, what is ETB? Or did you mean ETM (Embedded Trace Macrocell)?

Edit: 

I found some information about ETB ("Embedded Trace Buffer"). Arm's Cortex-M3 technical reference mention's ETB a few times without further explanation. CoreSight Trace Memory Controller Technical Reference Manual provides an example application of ETB.

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