Difficulties to establish a communication between a Spartan 6 with a Mini PCIe bus and ARM-Cortex A9 (IMX.6 architecture)

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Difficulties to establish a communication between a Spartan 6 with a Mini PCIe bus and ARM-Cortex A9 (IMX.6 architecture)

Contributor I

Hi !

I’m  trying to establish a communication between a Spartan 6 FPGA with a Mini PCIe bus and a board containing an ARM-cortex A9 (IMX6 architecture) running Linux kernel 4.13.

I want to use  RIFFA to communicate between the Spartan 6 FPGA and the Linux embeeded in the ARM processor using PCIe.

In order to do that, I first followed all the instructions in the RIFFA documentation and established a connection between a Spartan 6 FPGA bord with PCIe bus ( not Mini PCIe) and a host computer with a Windows OS and a x86 architecture , and everything was fine when using the  testuils.c  file.

 But, my main goal is to establish a connection between a Spartan 6 FPGA board with a Mini PCIe and a board with ARM cortex A9 processor. So I, generated the bit file supplied in the RIFFA Master folder and  I flashed the PROM of the FPGA in order to get bit file in the FPGA before booting the board with the embeeded Linux, then I checked the good  connection between the FPGA and the embeeded Linux using the lspci instruction and everything seemed to be ok at that point.

Now, the problem that I’m facing is that when I execute the testutil. code with a “0” argument it gives me the right informations about the my FPGA ( Vendor ID, Device ID, ….).

But, when I compile the testutils. code with a “ 1  0 “ arguments , 1 stands for “reset”  and 0 for “fpga ID”, it gives me a segmentation fault, so I tried to debug the code, I found the segmentation fault came from the read_reg function (from riffa_driver.c) that calls the readl function.

After a quick search on the internet, I found that the readl function tries to read from a virtual address which is sc->bar0.

Meanwhile, during boot time when initializing Riffa, the driver calls read_reg function with the same argument and it  doesn’t give any fault.

I also noticed that the base address register BAR0 was 0xFFFFFC00 when I wasconfiguring Xilinx PCIe  IP core and that Linux gives the  FPGA  the address BAR0 0x01100000  .   Is it normal that these two addresses are different ?

What are the changes that I should make in order to adapt RIFFA from x86  to the ARM processor ?


You can find below the screenshot of the error message:


unnamed (1).png

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