Dear All,
We are working on custom P2041 Board & we have following queries for the same.
On our custom p2041 board, we have used hard coded RCW (1_1000,16bit NOR flash as boot loc), uboot is programmed in NOR location 0XEFF4000 ( 768 KB file size ). UART1 from processor is used as console display. NOR flash memory map is same as that of 2041RDB.
We are not able to get the display on serial display console UART port 1.
U-boot start location is 0xeff40000.
However control does not go to this location but goes somewhere near at this address - 0xeff40068. And once it reaches this address it gives an error as "Scan Timeout".
Execution Sequence is as follows:
eff40000: dc.l 0xfff41956
eff40004: clrlslwi. r13,r9,17,8
eff40008: xoris r20,r27,0x2032
eff4000c: addic rsp,r17,13358
eff40010: addic rsp,r23,20847
eff40014: andi. r9,r18,0x512d
eff40018: insrwi. r4,r26,11,12
eff4001c: rlwinm. r17,r17,5,24,27
eff40020: frsqrte. fp31,fp6
eff40024: addi r11,r2,13921
eff40028: addic r17,r0,10308
eff4002c: oris r3,r11,0x2030
eff40030: addic. r25,r0,12848
eff40034: addic r9,r21,8237
eff40038: subfic rsp,r17,13626
eff4003c: addic rsp,r18,14898
eff40040: fcmpu cr7,fp20,fp0
eff40044: dc.l 0x00000000
eff40048: dc.l 0x00000000
eff4004c: dc.l 0x00000000
eff40050: lis r3,-48
eff40054: ori r3,r3,0x3f30
eff40058: li r0,0
eff4005c: stw r0,0(r3)
eff40060: stw r0,4(r3)
eff40064: mr rsp,r3
eff40068: bl 0xEFF4006C (0xeff4006c) ; 0xEFF4006C
eff4006c: mflr r12
What is the reason for the "Scan Timeout" error at 0xeff40068 location?
Also, we need to know how to write to LBCR register from u-boot configuration.
Because of this we are not getting the u-boot sequence succedded.
Can you test your board using a standalone debugger and this hard coded RCW?
Test SDRAM on your board using a memory test.
U-boot configuration file is located in the u-boot source folder: /include/configs. This folder contains the .h files for the different boards.
The u-boot binary image byte sequence is the following:
'VU-Boot 2015.01QorIQ-SDK-V1.8+g6ba8eed (Oct 26 2015 - 22:50:13)
It looks like that the first u-boot code offset is 0x68.
See u-boot binary image.
Have a great day,
Pavel
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