PCIe x2 Lane Reversal

[christiansielaf]

Hello all,is it possible to connect a x1 PCIe End Point at the second lane of an x2 PCIe Root complex? We are working on a customer LS1021A design and the SerDes are configured over the RCW with 0x50 (PCIe1 x2 / PCIe2 x1 / SGMII2). Our PCIe EP is connected to the SerDes Lane "B" of the PCIe1 Root Complex. The PCIe1 Root Complex should support lane reversal as well and so it should be OK ... or?We really appreciate your response.Best regards and thank you in advance,
Christian

[ufedor]

Response from the documentation team:

"The information was correct in Rev.1.0.

In rev 2.0 RM  unintentionally was changed. We are working on rev 3.0 RM and plan to correct the information and revert back to the rev 1.0 RM."

[christiansielaf]

Hello, ufedor,

please excuse the late response ... ;-).

We are now reaching the point where we try to use it exactly as I explained it in the first post. Before we only implemented a test during the manufacturing of our SoM with a long list of limitations.

So this means we operate an x1 endpoint on the second Lane of the x2 and it seems that the root complex isn't able to negotiate a stable link.

The LS1 interacts with the endpoint but the state machine does not reach L0. We bounce between S_POLL_ACTIVE and S_DETECT_WAIT.

We read in a former version that the lane reversal can also be manually adjusted.

The general control register of the lanes (SerFes_LNnGCR0) seams to be the right register for such a manually lane reversal but it doesn't work:

Please let me know what we can do to force a manual lane reversal of this x2. This seems to be the only way to use the second lane for our x1 endpoint.

We really appreciate your response.

Best regards and thank you in advance,

Christian

[ufedor]

Manual lane reversal is not supported - refer to the QorIQ LS1021A Reference Manual, Rev. 3.