LS1046A Watchdog timeout and SRS events not causing appropriate registers to indicate such event

[scottwelsh]

Hello, I am doing some watchdog testing with the LS1046A and have a similar issue to that of https://community.nxp.com/t5/Layerscape/LS1046A-watchdog-timeout/m-p/1552553#M11398.

That is, if the watchdog WT in WDOG1_WCR times out, upon the LS1046A's reset activities, I have determined that the WDOG1_WRSR register does NOT indicate the reset was due to watchdog timeout via the TOUT bit, bit 14. Bit 14 should be a 1 but it is not. That is, the WDOG1_WRSR register shows value 0x0010 (reserved bit 11 is high). Further, register RSTRQSR1 should show a 1 for bit 22, the CORE_WDOG1_RST_RR field to indicate, "Core watchdog reset request from WDOG1 is active." Register RSTRQSR1 instead shows 0x00004000. That is, the MBEE_RR bit is a 1.

Next, if I cause a hardware reset due to software reset request via setting the active low SRS bit (bit 11 to 0), where value 0 means Assert wdog_rst_b to COP. The system does reset but upon starting back up, I do NOT see bit SFTW (bit 15) of WDOG1_WRSR set to 1. The WDOG1_WRSR register is 0x0010.

[yipingwang]

RESET_REQ_B is an internal block request that asserts HRESET_B or PORESET_B. In your case, it is asserting PORESET_B, which resets the register to its default or initial state. If you want to see the source of the output reset assertion in WDOGx_WRSR, connect your RESET_REQ_B to HRESET_B.