LS1043A MDC/MDIO AC timing sequence

[shawn_tao]

LS1043A 中EMI1_MDC/MDIO接口时序问题：

根据手册147页的示意图，写时序：EMI1在MDC上升沿延迟tMDKHDX后数据翻转，但是示波器实际测量MDC是在下降沿打出数据，如下图：这是手册描述问题还是有什么配置呢？

另外，读时序时：PHY在MDC的上升沿经过一段延迟后扇出数据，CPU也是利用这个上升沿采样吗？还是可以配置CPU使用下降沿采样？

[ufedor]

MDIO behaviour in the provided trace is valid.

Please check MDC to MDIO delay tMDKHDX controlled by the MDIO_CFG[MDIO_HOLD].

Please check whether MDIO_CFG[NEG]=1 then LS1043A will transmit data on falling edge of the clock.

This implies with MDIO_CFG[NEG]=1 the tMDKHDX should be measured with respect to the falling edge of clock.

> can I configure the CPU to use falling edge sampling?

No.

[shawn_tao]

where could I find these registers in the doc: QorIQ LS1043A Reference Manual Rev. 4, 6/2018.

Thanks.

[ufedor · Accepted solution]

Please refer to the QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual.