LS1021A - Custom Board NAND Issue- No NAND device Found

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LS1021A - Custom Board NAND Issue- No NAND device Found

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sanjuvarghese
Contributor II

Hi,

I am facing an issue in my custom ls1021a board. We have a NAND flash (1GB) on the AD0-AD7 IFC Bus. While booting, the Device ID and the Manufacture ID is coming as 0,0. I have identified that the "nand_scan_ident(mtd, 1, NULL);"  function is unable to find the device. NAND configuration in my config file is 

#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE        0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS    CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_CSPR_EXT    (0x0)

#define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
        | CSPR_PORT_SIZE_8    \
        | CSPR_MSEL_NAND    \
        | CSPR_V)

#define CONFIG_SYS_NAND_AMASK    IFC_AMASK(128*1024)
#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN  \
        | CSOR_NAND_ECC_DEC_EN   \
        | CSOR_NAND_ECC_MODE_4   \
        | CSOR_NAND_RAL_3    \
        | CSOR_NAND_PGS_2K   \
        | CSOR_NAND_SPRZ_64    \
        | CSOR_NAND_PB(64) )
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_FTIM0        (FTIM0_NAND_TCCST(0x7) | \
            FTIM0_NAND_TWP(0x18)   | \
            FTIM0_NAND_TWCHT(0x7) | \
            FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1        (FTIM1_NAND_TADLE(0x32) | \
            FTIM1_NAND_TWBE(0x39)  | \
            FTIM1_NAND_TRR(0xe)   | \
            FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2        (FTIM2_NAND_TRAD(0xf) | \
            FTIM2_NAND_TREH(0xa) | \
            FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0
#define CONFIG_SYS_NAND_BASE_LIST    {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE    1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE    (512 * 1024)
#define CONFIG_SYS_CSPR0_EXT        CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0        CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0        CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0        CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0        CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1        CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2        CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3        CONFIG_SYS_NAND_FTIM3

The u-boot output is

U-Boot 2015.01+ls1+g3281947 (Jan 28 2016 - 21:31:43)

CPU:   Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)

Clock Configuration:

       CPU0(ARMV7):1000 MHz,

       Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),

Reset Configuration Word (RCW):

       00000000: 0608000a 00000000 00000000 00000000

       00000010: 00000000 08407900 40105a00 21046000

       00000020: 00000000 00000000 00000000 080b8000

       00000030: 20024805 001b3340 00000000 00000000

Board: LS1021AIOT

I2C:   ready

DRAM:  1 GiB

Using SERDES1 Protocol: 0 (0x0)

THe Manufacture Id is 0,0

No NAND device found

0 MiB

MMC:   FSL_SDHC: 0

SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total 64 MiB

EEPROM: Read failed.

PCIe1: Root Complex no link, regs @ 0x3400000

PCIe2: disabled

In:    serial

Out:   serial

Err:   serial

SEC0: RNG instantiated

SATA link 0 timeout.

AHCI 0001.0300 1 slots 1 ports ? Gbps 0x1 impl SATA mode

flags: 64bit ncq pm clo only pmp fbss pio slum part ccc

scanning bus for devices...

Found 0 device(s).

=>

Can anyone help me to solve the issue?

Thanks in advance.

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1 解答
3,369 次查看
ufedor
NXP Employee
NXP Employee

In the provided schematics IFC_AD[0:7] are connected to IO[0:7] which is not correct - should be IO[7:0].

Refer to the attached screenshot from the LS1021ARM.

在原帖中查看解决方案

8 回复数
3,369 次查看
shunpinglin
Contributor III

hello,

       I have also custom ls1021a board with nand flash. Now we need boot from nand flash. except modifying the board configure file, what files do I modify? Do the rcw and pbi have modify?

Thank you!

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ufedor
NXP Employee
NXP Employee

Please provide the processor connection schematics as searchable PDF.

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sanjuvarghese
Contributor II

Hi,

Thanks For the Response.

Please find the NAND flash interface section in the PDF attached.

Thanks

Sanju

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3,370 次查看
ufedor
NXP Employee
NXP Employee

In the provided schematics IFC_AD[0:7] are connected to IO[0:7] which is not correct - should be IO[7:0].

Refer to the attached screenshot from the LS1021ARM.

3,368 次查看
sanjuvarghese
Contributor II

Hi,

Thanks for the Reply. That was the issue. The NAND is working now in the u-boot. A s I am getting the Manufacture ID.

But still the Linux is unable to find the NAND flash. As the error is always coming as

"fsl,ifc-nand 0.ifc: fsl_ifc_nand_probe: failed to get resource

fsl,ifc-nand: probe of 0.ifc failed with error -22"

The Device Tree Bindings shown below

ls1021a.dtsi

----------------

ifc: ifc@1530000 {

                        compatible = "fsl,ifc","simple-bus";

                        reg = <0x0 0x1530000 0x0 0x10000>;

                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;

}

ls1021aiot.dtsi :

---------------------

&ifc {

        #address-cells = <2>;

        #size-cells = <1>;

        ranges = <0x0 0x0 0x7e800000 0x10000>;

        status = "okay";

       nand@0{                                  

                #address-cells = <1>;

                #size-cells = <1>;

                compatible = "fsl,ifc-nand";

               reg = <0x0 0 0x10000>;

                bank-width = <1>;

                device-width = <1>;

        };

In the fsl-ifc-nand.c probe function,   of_address_to_resource(node, 0, &res); is always failing.

Can you help us to solve the issue in linux?

Thanks in advance

Sanju

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ufedor
NXP Employee
NXP Employee

Please explain how exactly you fixed the IFC_AD[0:7] connection issue.

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sanjuvarghese
Contributor II

Hi,

For testing we removed all the 0 Ohm resistors from the IFC AD lines and connected it reversely as you mentioned. In U-boot, NAND chip is getting detected and showing 1024MiB as expected. I can erase/write/read the NAND chip from u-boot. But linux is not detecting the chip.

Any Idea on this Issue? 

Is there any other way to change the functionality of these pins without reversing it externally?

Thanks

Sanju

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ufedor
NXP Employee
NXP Employee

The described connection modification is correct.

It will be more convenient to create new thread for the Linux-related questions.

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