Booting from Nor Flash on Custom LS1043A Board

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Booting from Nor Flash on Custom LS1043A Board

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Ishizak
Contributor II

I'm trying to boot my custom LS1043A board from Nor Flash connected to the IFC interface, but no success.

After the PORESET_B is negated, the POR Status Register 1 is set to 0x12FF_FFFF (16-bit Nor Flash) and it seems good.

And at that point, the SYSCLK has been stabilized.

However, there is no IFC_CS0 activities after the PORESET_B is negated.

Can anyone suggest what to investigate?

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6 Replies

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Ishizak
Contributor II

Sorry for my late response.

I have fixed the problem.

I checked the TRST_B and related signals/logics.

I found a problem in handling the PORESET and SYSRESET.

Thank you for your suggestions.

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Ishizak
Contributor II

Thanks for the support.

 > 1) SYSCLK or DIFF_SYSCLK is applied and properly selected by the cfg_eng_use0 (IFC_WE0_B).

Checked. They seemed OK.

 > 2) TRST_B is pulsed low during POR sequence.

I will check it.

 > 3) All signals having note 5 in the QorIQ LS1043A, LS1023A Data Sheet, "Pinout List by bus" are not low during POR.

Checked. They seemed OK.

 > 4) IFC_OE_B (cfg_eng_use1) is high during POR.

Checked. They seemed OK.

 > 5) You wrote:

>> 0x12FF_FFFF (16-bit Nor Flash)

> Are you using internal latch based asynchronous NOR device?

The NOR device installed on the board is MT28FW02G. I think the reset configuration is set properly.

 

Any further comments and suggestions will be appreciated.

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ufedor
NXP TechSupport
NXP TechSupport

Please provide the processor connection schematics as searchable PDF for inspection.

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240 Views
Ishizak
Contributor II

I'm sorry but I cannot provide you with the actual schematics.
It might be possible to provide the very limited portions of them, though.
Is it possible for you to clarify the specific signals of interest? (Same as those you mentioned in the previous reply?)

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ufedor
NXP TechSupport
NXP TechSupport

For inspection are needed only pages showing LS1043 connections.

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ufedor
NXP TechSupport
NXP TechSupport

Points to check:

1) SYSCLK or DIFF_SYSCLK is applied and properly selected by the cfg_eng_use0 (IFC_WE0_B).

2) TRST_B is pulsed low during POR sequence.

3) All signals having note 5 in the QorIQ LS1043A, LS1023A Data Sheet, "Pinout List by bus" are not low during POR.

4) IFC_OE_B (cfg_eng_use1) is high during POR.

5) You wrote:

> 0x12FF_FFFF (16-bit Nor Flash)

Are you using internal latch based asynchronous NOR device?