These instructions explain how to use the CodeSourcery GNU tools to build a LWIP project and variant. GNU builds are based on the free CodeSourcery Codebench Lite version. Download the CodeSourcery Lite GNU tools Prior to building the code, you'll need to CodeSourcery GNU tools. These can be download from Mentor Graphics. There are multiple versions of the tools that can be download. Make sure you download the EABI version of the tools with CodeBench. These will be identified similar to "Sourcery CodeBench Lite 2011.09-69 for ARM EABI". The IA32 Windows Installer version was used to generate the projects included in the LWIP packages. After the tools are downloaded, install the tools onto your build machine. Build system and source code modifications Before you can build the projects, a few manual modifications of the source code and a few make related files are needed. lpc177x_8x_emac.c Locate the lpc177x_8x_emac.c and open it for editing. Wrap "#if 0/#endif" clauses around the ENET_IRQHandler function. This will prevent build problems when using the interrupt handler of the same name as part of the LWIP driver. makeconfig Locate the makeconfig file in the makesection folder.If needed, change the path and version number to what's been installed for your host machine. #GNU_INSTALL_ROOT    =C:/Program Files (x86)/CodeSourcery/Sourcery G++ Lite GNU_INSTALL_ROOT    =C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI GNU_VERSION               =4.3.3 make.LPC177x_8x.gnu Locate the make.LPC177x_8x.gnu file in the makesection/LPC177x_8x folder. Make changes as needed to this file for your build. For example, only the changes below were needed. OPTIM            = s CC                 = $(GNUTOOLS)/arm-none-eabi-gcc #CC               = $(GNUTOOLS)/arm-none-eabi-gcc-$(GNU_VERSION) Build procedure Add make tools to system environment path Once the changes have been made, open up a CMD (cmd.exe) shell for your Windows host machine. In the shell, switch to the directory with the example project (ie, ea1788_tcpecho_sa) and then into the gnu subfolder in that project. Run theaddtoolpath.bat script to add the tools path to your shell's environment. C:\dev\git\lwip_work\updated\lpc177x_8x\lwip_lpc\nxpcommon\examples\ea1788\ea1788_tcpecho_sa\gnu>set PATH=..\..\..\..\..\..\makesection\tools;..\..\..\..\..\..\makesection\tools;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files\TortoiseGit\bin;C:\Keil421\ARM\BIN40;C:\Program Files (x86)\doxygen\bin;C:\Program Files (x86)\Enterprise Vault\EVClient\;C:\Program Files (x86)\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI\bin;C:\Program Files (x86)\CodeSourcery\Sourcery G++ Lite\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files\TortoiseGit\bin;C:\Keil421\ARM\BIN40 C:\dev\git\lwip_work\updated\lpc177x_8x\lwip_lpc\nxpcommon\examples\ea1788\ea1788_tcpecho_sa\gnu> Make the image Then type make to build the project. If your project builds without errors, you should get a hex file that can be programmed into the board usng the Flash Magic tool. port/sdram_k4s561632j.o C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../BoardSupport/sdram_mt48lc8m32lfb5.o C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../BoardSupport/sensor_smb380.o C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../BoardSupport/transceiver_sn74lvc16245.o C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../BoardSupport/uda1380.o   lpc_emac.o lpc_emac_zcbuffs.o lpc_phy.o lpc_debug.o sys_arch.o Serial.o lpc177x_8x_systick_arch.o retarget.o ea1788_board.o tcpecho_sa_app.o def.o dhcp.o dns.o init.o mem.o memp.o netif.o pbuf.o raw.o stats.o sys.o tcp.o tcp_in.o tcp_out.o timers.o udp.o autoip.o icmp.o igmp.o inet.o inet_chksum.o ip.o ip_addr.o ip_frag.o etharp.o echo.o  -static -mcpu=cortex-m3 -mthumb -mthumb-interwork -Wl,--start-group  -L'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/lib/gcc/arm-none-eabi/4.3.3/thumb2' -L'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/arm-none-eabi/lib/thumb2' -lc -lg -lstdc++ -lsupc++  -lgcc -lm  -Wl,--end-group   -Xlinker -Map -Xlinker \ea1788_tcpecho_sa.map -Xlinker -T   linker/ldscript_dram_zc_gnu.ld -o ea1788_tcpecho_sa.elf 'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'/arm-none-eabi-objcopy -O ihex  ea1788_tcpecho_sa.elf ea1788_tcpecho_sa.hex 'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'/arm-none-eabi-objcopy -O srec  ea1788_tcpecho_sa.elf ea1788_tcpecho_sa.srec C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mkdir -p GCC\Flash C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mv -f ea1788_tcpecho_sa.map GCC\Flash\ea1788_tcpecho_sa.map C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mv -f ea1788_tcpecho_sa.elf GCC\Flash\ea1788_tcpecho_sa.elf C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mv -f ea1788_tcpecho_sa.hex GCC\Flash\ea1788_tcpecho_sa.hex C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mv -f ea1788_tcpecho_sa.srec GCC\Flash\ea1788_tcpecho_sa.srec 'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'/arm-none-eabi-size GCC\Flash\ea1788_tcpecho_sa.elf    text    data     bss     dec     hex filename   70376     216 4611064 4681656  476fb8 GCC\Flash\ea1788_tcpecho_sa.elf Once the image has been built, you can use Flash Magic to program the image into internal FLASH using the generated HEX file.

If you accidentally erase the kick start or S1L boot loaders on the Phytec LPC3250 board, this procedure can be used to restore them. Note the boot loaders provided in this restoration method might be newer than the versions provided with the Phytec board. The original versions of the boot loaders can also be downloaded from Phytec's website. Restoration of the boot loaders on the board require no special hardware (ie, JTAG) and are performed with boot loaders and tools built or included in the LPC32x0 Common Driver Library. However, you will need a PC with a serial port to perform the update procedure. Restoring the kick start loader and S1L is a 2-step process. The kick start loader is restored first and then S1L is restored. The serial loader is used to transfer the application and the burner images (which is used to program the application into NAND FLASH). The LPC32x0 will automatically burn the image into NAND FLASH after it has been downloaded and then provide a status. Step 1: Download the pre-built boot software and restoration images for the Resource page. Step 2: Extract the files on a Windows based PC Step 3: Connect a serial cable between the Phytec boards' lower serial connector and the PC Step 4: Start the Serial loader software (LPC3250_Loader.exe) included in the pre-built boot software package. Step 5: Setup the 'Primary boot (IRAM)' file in the Serial loader to the burner_kickstart_nand_small_block_rvw.bin file. Setup the 'Secondary Executable (SDRAM)' file in the Serial loader to the kickstart_nand_small_block_rvw.bin file. Verify that the Comport control selection matches the COM part on the PC that is connected to the Phytec board. NOTE: The pre-built binaries may have slightly different names than those listed in steps 5 and 7, depending on the tool used to build the binaries. If the binaries were build with GNU instead of Realview, the 'rvw' field in each name will contain the 'gnu' identified instead. Change the filenames as necessary for you binaries you have.   Step 6: Press the 'Load bin's / Start primary' button on the Serial loader and power on the board. The burner image and the kickstart loader image should transfer to the board and the kickstart loader will then be programmed into NAND FLASH block 0 for boot from the boot ROM by the burner application. After the files have transferred, press the 'Enable terminal mode' button to see the program status. In the Status / Terminal output window of the Serial loader tool, you should see the following output.   Waiting for BootID? .. þ5 .. found! Sending 'A' .. done! Expect 2-nd BootId? .. 5 .. found! Sending 'U','3'.. done! Expect 'R' .. R .. found! Sending startaddress .. done! Sending size .. done! Sending code .. done! --- Loading Secondary executable --- Wait for 'X' .. X .. found! -- Sending command .. p ..done! Sending startaddress .. done! Sending size .. done! Wait for acceptance from primary boot .. o ..OK! Sending code .. done! Expect final 't' .. t .. found, ---- Secondary Executable loaded. --- --- Enabling terminal mode --- Formatting blocks... Format complete Writting kickstart into flash... Verifing data......Successfully NAND flash is programmed Successfully Step 7: Setup the 'Primary boot (IRAM)' file in the Serial loader to the burner_s1app_nand_small_block_rvw.bin file. Setup the 'Secondary Executable (SDRAM)' file in the Serial loader to the s1l_from_kick_full_rvw.bin file. Verify that the Comport control selection matches the COM part on the PC that is connected to the Phytec board.   Step 8: Press the 'Load bin's / Start primary' button on the Serial loader and reset the board. The burner image and the S1L image should transfer to the board and S1L will then be programmed into NAND FLASH block 1 (and on) for boot from the kickstart loader. After the files have transferred, press the 'Enable terminal mode' button to see the program status. In the Status / Terminal output window of the Serial loader tool, you should see the following output.   Waiting for BootID? .. 5 .. found! Sending 'A' .. done! Expect 2-nd BootId? .. 5 .. found! Sending 'U','3'.. done! Expect 'R' .. R .. found! Sending startaddress .. done! Sending size .. done! Sending code .. done! --- Loading Secondary executable --- Wait for 'X' .. X .. found! -- Sending command .. p ..done! Sending startaddress .. done! Sending size .. done! Wait for acceptance from primary boot .. o ..OK! Sending code .. done! Expect final 't' .. t .. found, ---- Secondary Executable loaded. --- --- Enabling terminal mode --- Formatting blocks... Format complete Writting S1 image into flash... NAND flash is programmed Successfully Step 8: Close the Serial loader and open a terminal program, then reset the board Close the serial loader tool and open a terminal program such as Teraterm. Reset the board and S1L should start.   5 Phytec 3250 Board Build date: May 21 2010 12:43:21 PHY3250>

These examples show several possible uses for the DFUSec programming feature of the tool. LPC1857 single bootable image programmed in internal FLASH This example shows how to burn a snigle bootanle image into internal FLASH. When booting from internal FLASH, the boot address is 0x1A000000. The image has been linked for this address with data in IRAM. This operation requires a simple 1-step programming sequence. The operation will do the following: Erase just the area of internal FLASH dedicated to the bootable image (we'll use 64K starting at address 0x1A000000) Program the image (up to 64K) into address 0x1A000000 DFUSec configuration The image below shows the DFUSec configuration and a successful program cycle. This uses the LPC18xx/43xx internal FLASH programming algorithm. The 2nd file box contains the path/filename to the image file to program. The image file already includes the checksum and CRP. The address (0x1A000000) and size (0x10000) designate the erase region, program address, and maximum program size. Since the 'Erase region before programming' option is selected, the FLASH at address 0x1A000000-0x1A00FFFF will be erased prior to programming. After rease completes, the image will be sent to the board (in small chunks) and programmed into FLASH. If the image exceeds 64K (specified by the same size parameter used for region erase), an error will be generated, even if FLASH extended beyond the 64K limit specified. LPC1857 multiple images in internal FLASH This example shows how to burn multiple images into different location in internal FLASH. Although this example is shown using the Keil MCB1857 board, the example can easily be used to separately program (or update) M0 and M4 images into different location in internal FLASH for the LPC4350 dual core device! Either image can be updated later without erasing the entire device or the other image. This operation requires a 2-step programming sequence. Step 1 will erase the entire device and program image_1 into bank A. Step 2 will program image_2 into bank B. Optionally, with step 2, we can program image_2 into another area of bank A if needed. Step 1 DFUSec configuration The internal FLASH programming algorithm is used with the image_1.bin program file. Step 1 will erase the entire device (both bank A and B) before programming. Then image_1 will be placed at the bootup address (0x1A000000). We'll limit the image size to a maximum of 128K for programming. The configuration is show below: Step 2 DFUSec configuration The internal FLASH programming algorithm is used with the image_2.bin program file. Step 2 will place image_2 at the 2nd bank address (0x1B000000). We'll limit the image size to a maximum of 16K for programming. The configuration is show below: Screenshot of the completed DFUSec 2-step program operation

Description This example implements a mass storage class device that operates on a FAT12 volume stored in internal RAM. The size of this volume is set by the constant DATA_RAM_PHYSICAL_SIZE defined in DataRam.h Compiler build configurations The software that makes up this example is designed to run on many different development boards. Therefore the compiler must be configured to build an image that is targeted to the development board you are using. This section explains how to set these build configurations for each of the supported compilers.   LPCXpresso IDE Configure projects   right click on the BSP project in the project explorer window   click Build Configurations->Set Active->(see configuration in table below)   repeat these steps with the CDL, nxpUSBlib, and Example_MassStorageDevice Configure MCU   right click on the Example_MassStorageDevice project in the project explorer window   click Properties->C/C++ Build->MCU settings->(see configuration in table below) Configure the indexer    click Window->Preferences->C/C++->Indexer->Use active build configuration BSP CDL nxpUSBlib Example_MassStorageDevice MCU LPC1850  / Hitex LPC18xx_HITEX LPC18xx LPC18xx_Device LPC18xx LPC1850 LPC4330  / Xplorer LPC4330_Xplorer LPC18xx LPC18xx_Device LPC18xx LPC4330 LPC4350  / Element14 LPC1435_ELEMENT14 LPC18xx LPC18xx_Device LPC18xx LPC4350 LPC11U14 / LPCXpresso LPC11Uxx_LPCXpressoRevB LPC11Uxx LPC11Uxx_Device LPC11Uxx LPC11U14 LPC11U14 / MCB1000 LPC11u14_MCB1000 LPC11Uxx LPC11Uxx_Device LPC11Uxx LPC11U14 LPC1768  / MCB1700 LPC1768_MCB1700 LPC17xx LPC17xx_Device LPC17xx LPC1768 LPC1768  / LPCXpresso LPC17xx_LPCXpressoRevB LPC17xx LPC17xx_Device LPC17xx LPC1768 NOTE: The LPC18xx CDL is used with boards that hold LPC43xx parts. This is done because the LPC43xx CDL is currently experimental. The LPC18xx USB library is used because both parts share the same controller.   Keil uVision 4 IDE Configure a Batch Build     click on Project->Batch Build...   expand the BSP project to display a list of project targets   select the project target by checking the appropriate checkbox (see target list in table below)   repeat these steps with the CDL, nxpUSBlib_Device, and Example_MassStorageDevice BSP CDL nxpUSBlib_Device Example_MassStorageDevice LPC1850  / Hitex HITEX1800 LPC18xx LPC18xx_Device HITEX1800 LPC1768  / MCB1700 MCB1700 LPC17xx LPC17xx_Device MCB1700 LPC11U14 / MCB1000 MCB1000 LPC11Uxx LPC11Uxx_Device MCB1000   Board connections and configurations   LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  older A2 design schematic ./BSP/schematics/HITEX_SCM_LPC1850EVA-A2-2.pdf   Connect the JTAG to the 20 pin receptacle marked X4 JTAG Connect the type-B end of a USB cable to the receptacle marked X2. Plug the type-A end of this cable into a PC LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  newer A4 design schematic ./BSP/schematics/HITEX_Final_LPC1850EVA-A3.pdf   LPC4330_Xplorer (NGX Xplorer Evaluation Board with LPC4330) Connect the JTAG to the 10 pin receptacle marked J2 Connect the micro-b end of a USB cable to the receptacle marked USB0. Plug the type-A end of this cable into a PC   LPC1435_ELEMENT14 (Element 14 gaming board with LPC4350) Connect the JTAG to the 10 pin receptacle marked J6 Connect one end of a type-A to type-A USB cable to the receptacle marked USB0. Plug the other end of this cable into a PC   LPC11u14_MCB1000 (Keil MCB1000 development board) schematic: ./BSP/schematics/mcb1000-schematics.pdf   Jumpers:   J4 = 2-3      (UCON - PIO0_6 pulls D+ high)   J2 = 1-2          (VDD  - core power)   J5 not installed  (ISP  - ISP via COMM)   J6 not installed  (RST  - ISP via COMM) Connect the JTAG debugger to the 10 pin Cortex Debug connector labeled J3 Connect the type-B end of a USB cable to the type-B recepticle and the type-A end of the cable to the USB receptacle on a PC Once the USB cable is connected to the board the following LEDs should be illuminated:     Power     All 8 LEDs in PIO2   LPC1768_MCB1700 (Keil MCB1700 development board) schematic: ./BSP/schematics/mcb1700-schematics.pdf   Jumpers:   E/U    = 1-2  (Ethernet/USB)   UMODE  = 1-2  (USB Device Mode)   D-     = Device   D+     = Device   VBUS   = 1-2   VDDIO  = 1-2   VDDREG = 1-2   Connect the JTAG debugger to the 20 pin JTAG or 10 pin Cortex Debug connector. Connect the type-B end of a USB cable to the type-B recepticle labeled 'Device' and the type-A end of the cable to the USB receptacle on a PC. Once the USB cable is connected to the board the following LEDs should be illuminated:     Power     100MHz     USC (LED indicates a USB soft connect from P2.9)    LPC11Uxx_LPCXpressoRevB (LPCXpresso LPC11Uxx on the LPCXpresso Rev B base board) schematic: ./BSP/schematics/lpcxpresso.lpc11u14.schematic.pdf   Running this example on the LPCXpresso LPC11U14 can be done one of two ways:   1. LPCXpresso LPC11U14 stand-alone       Connect the type-B end of a USB cable to the mini receptacle on the LPCXpresso board labeled J8 and the type-A end to the USB receptacle on a PC   2. LPCXpresso LPC11U14 plugged into the LPCXpresso base board Rev B       Plug the LPCXpresso LPC11U14 board into the connector labeled J4 on a LPCXpresso base board Rev B       Configure the base board according to the user's guide from Embedded Artists       Connect the mini type-B end of a USB cable to the receptacle on the base board labeled X1 and the type-A end to the USB receptacle on a PC       Once the USB cable is connected to the board the following LEDs should be illuminated:           LED25  (vbus)          LED26  (3.3v rail)         For both configurations the JTAG debugger is connected to the mini USB receptacle labeled J3 on the LPCXpresso LPC11U14 board   LPC17xx_LPCXpressoRevB (LPCXpresso LPC17xx on the LPCXpresso Rev B base board) schematic: ./BSP/schematics/LPCXpressoLPC1769revB.pdf   Running this example on the LPCXpresso LPC1769 can be done one of two ways:   1. LPCXpresso LPC1769 stand-alone. Solder a type-B USB receptacle onto the board and wire it up. See included schematics for details. Connect the type-B end of a USB cable to the receptacle on the LPCXpresso board and the type-A end to the USB receptacle on a PC   2. LPCXpresso LPC1769 plugged into the LPCXpresso base board Rev B. Plug the LPCXpresso LPC1769 board into the connector labeled J4 on a LPCXpresso base board Rev B. Configure the base board according to the users guide from Embedded Artists. Connect the mini type-B end of a USB cable to the receptacle on the base board labeled X1 and the type-A end to the USB receptacle on a PC.    Once the USB cable is connected to the board the following LEDs should be illuminated:       LED25  (vbus)       LED26  (3.3v rail)         For both configurations the JTAG debugger is connected to the mini USB receptacle labeled J3 on the LPCXpresso LPC1769 board. PC configuration Use a PC running Windows XP, Vista or 7 Connect the type-A end of the USB cable that is connected to the board into one of the USB receptacles on the PC Open a Windows File Explorer window Build and debug the example LPCXpresso IDE In the project explorer window of the IDE right click on the Example_MassStorageDevice project and select Debug As->C/C++ MCU Application In the main window of the IDE click Run->Resume to start running the application   Keil uVision 4 IDE In the Batch Build window, select the project targets as described in Compiler Build Configurations and then click Build In the main window of the IDE click Debug->Start/Stop Debug Session click Debug->Run   How this example runs and what to look for When the example is run and the board is connected to a PC with a USB cable it will enumerate on the PC as a mass storage device and show up in your Windows file explorer as a drive with the volume label "nxpUSBlib".   The drive will contain a single file called "README.TXT" which contains the text "This is a USB Memory Device demonstration. " Design notes This Mass Storage Device example defines a virtual drive size and a physical drive size. These numbers are defined in the file DataRam.h and look like this:   #define DATA_RAM_START_ADDRESS          0x20080000 #define DATA_RAM_PHYSICAL_SIZE            0xc00

To build a project for Keil, select the uvproj file for the example you want to build and deploy. The project will open up in the Keil uVision4 IDE. For the project, select the build variant you want to build. Press F7 to start the build. The image can be programmed into the board's internal FLASH (if it's a FLASH image) using the Flash menu and selecting Download. Optionally, you can download and debug the program using the Debug menu and selecting "Start/stop debug session". Note you need a Keil ULINK JTAG/SWD debugger to debug or download code. If you get an error attempting to program FLASH, check that the FLASH algorithm selected for the device is correct by selecting the FLASH menu and then selecting the Settings box. On the Flash Target driver setup display, select the LPC17xx IAP 256K Flash algorithm for programming. If a debugger isn't available, you can use Flash Magic with the created hex file to burn the image into the board. Before attempting to run Flash Magic, make sure the LPC17xx device is in ISP mode by holding down the SW6 while pressing and releasing the reset button.

Introduction Electric motors drive motion in all kinds of applications, from washing machines and exercise treadmills to the HVAC (heating, ventilation, and air conditioning) systems in commercial buildings. The drawback is that they can consume quite a bit of energy. Refrigeration for homes and offices accounts for nearly 10% of the world's energy usage, and roughly 60% of all the electrical power generated in the US is consumed by electric motors. Designers are using 32-bit MCUs to add sophisticated motor control to their systems, and thereby improving efficiency, reducing cost, and saving energy. In consumer appliances, for example, the trend is away from motors that cycle on and off (and require high starting torque) and more toward smaller, electrically-controlled motors that operate continuously, at a slower speed, and adapt their torque (and speed) to maintain the desired performance. These new, electrically-controlled motors save power and, as an added bonus, reduce maintenance and extend service life because they use fewer mechanical components. NXP Advantage Design challenges for electric motors include finding ways to improve accuracy, increase speed, reduce power consumption, limit electromagnetic interference (EMI), lower cost, and expand the number of tasks the system can perform. NXP's 32-bit ARM MCUs meet all of these challenges. They offer ample performance with integrated options specially tailored to motor control: NXP Product Families for Motor Control All the ARM MCUs integrate general-purpose PWMs for basic motor control. Five families offer dedicated motor-control PWMs (LPC43xx, LPC18xx, LPC17xx, LPC32x0, LPC29xx). Four families offer a Quadrature Encoder Interface (QEI) for very accurate orientation, feedback, and control (LPC43xx, LPC18xx, LPC17xx, LPC29xx). Four families offer 6-channel PWMs for control of three-phase motors (LPC21xx, LPC22xx, LPC23xx, LPC24xx). Two families offer the proprietary State Configurable Timer (SCT) subsystem, which is comprised of a timer array with a state machine enabling complex functionality including event-controlled PWM waveform generation, ADC synchronization, and dead time control. This timer subsystem gives embedded designers increased flexibility to create user-defined waveforms and control signals (LPC43xx, LPC18xx). Many of today's motor-control applications use 8- or 16-bit MCUs or DSPs. Designers looking to upgrade to 32-bit performance will find plenty of choices in NXP's portfolio. Our MCUs offer a range of motor-control options, in a wide variety of formats: Package sizes from 48 to 320 pins Memories from 8KB to 1MB of flash, with flashless options Clocks from 1kHz to 267MHz DSP capabilities with the LPC4300 Cortex-M4 series Integrated ADCs in 10- and 12-bit formats Built-in peripherals, including Ethernet, USB, LCD, and CAN Products Comparison Table Below, are NXP's ARM MCUs featuring dedicated PWMs for motor control and Quadrature Encoder Interfaces (QEIs): Product(s) ARM Core Motor Control PWM (# Channels) Quadrature Encoder Interface State Configurable Timer LPC43xx Cortex-M4 9 X X LPC18xx Cortex-M3 9 X X LPC17xx Cortex-M3 6 X LPC32x0 ARM926EJ 9 LPC29xx ARM968E-S 24 X Cortex-M3-Based MCUs with Dedicated Motor Control PWMs Click here for more information: ARM Cortex-M3 Core MCUs ARM9-Based MCUs with Dedicated Motor Control PWMs Click here for more information: ARM9 Core MCUs Support LPCXpresso Motor Control Kit The LPCXpresso Motor Control Kit, developed in partnership with Embedded Artists, is ideal for prototyping your motor control project or when you wish to learn more about motor control. The board can be directly controlled by LPCXpresso LPC1114/LPC1343/LPC1768 target boards. With this universal platform, it is possible to control BLDC, BLAC, stepper, and dual-brushed DC motors. The kit comes with the LPCXpresso Motor Control Board, an LPCXpresso LPC1114 target board with LPC-Link JTAG (supported by the LPCXpresso IDE), a BLDC motor with hall sensors, and a 24V/60W power supply. The kit is available through NXP's distribution network. Embedded Artists LPCXpresso Motor Control Kit Multimedia Presentation Software Sample Code Bundle for LPC213x/LPC214x Peripherals using ARM's RealView (Mar 8, 2006) Sample Code Bundle for LPC213x/LPC214x Peripherals using Keil's μVision (Dec 18, 2008) Sample Code Bundle for LPC23xx/LPC24xx Peripherals using Keil's μVision V1.60 (Mar 10, 2009) TN0700x Sample Code V1.00 (Jun 22, 2007)   More Information   Links Microcontrollers USB Support   Disclaimer Software from NXP referenced on this page is provided AS-IS by NXP Semiconductors. NXP Semiconductors does not support or warrant the software contained herein for any purpose other than for informational use.

Introduction There are several options for Software Encryption running on the different LPC ARM microcontrollers. Some of these options are offered for free from NXP, while others are free open-source solutions and still others are royalty-based encryption offerings from 3rd parties. These different solutions offer trade-offs between costs, memory footprint, performance and support levels, so please choose the library that best meets the needs of your project. Links Application Note: AES encryption and decryption software on LPC MCUs (zip file) Cypherbridge Systems: uSSL and CDK Real Time Logic: SharkSSL Library Real Time Logic: ARM Cortex-M0 Benchmarks Security Innovation: Encryption Libraries for LPC2000 ARM7 LPC1200 Bootloader from Metratec Polar SSL Open-Source Encryption Library Cya SSL Open-Source Encryption Library "All other trademarks, product names, trade names, and logos used within these pages are the property of their respective holders."

Introduction This page gives a quick overview of the available IOH libraries. A description of the library, its specifications and its requirements are summarized on this page. The the following downloads are attached to the community post below. Full library documentation. The IOH pre-compiled libraries. 1 or more application example source-code/projects per library (LPCXpresso, Keil MDK, IAR EWARM). The following libraries are currently available: Serial-interface emulation DALI I2S master I2C master UART CPU-cycle saving libraries CRC Windowed Comparator DMA The serial-interface emulation allows easy addition of one more serial interface to the LPC11x37H microcontrollers.The CPU-cycle saving libraries offer CPU-offloading for certain tasks, which can be used for lower power consumption (ARM core put in sleep mode), or for high performance (ARM executing other tasks in parallel). DALI The I/O Handler DALI library provides functionality to emulate a DALI master using the I/O Handler hardware block. DALI is a technical standard for network-based systems that control lighting in e.g. building automation. The IOH library allows to handle a large portion of the DALI standard autonomously by the I/O Handler peripheral with zero to very little CPU load.The library integrates a large portion of the DALI interface. The easy-to-use API is non-blocking and only passes the data to be transmitted to the I/O Handler.After a transfer has been initiated, the I/O handler takes care of the Manchester encoding and generation of edges on an I/O pin without any CPU involvement. The IOH ensures the mandatory wait time (settling time) between frames is honored and keeps track of the DALI input pin to watch for any response. Besides the supported polling mode to test if a transmission has finished, an interrupt is also generated at the end of every transmission. Data indicating whether the slave has send back a response and what this response is, can be accessed through another API call. Specifications Master mode only (a future library update may add slave support). Manchester encoding/decoding, pin I/O and settling time all handled by IOH with zero CPU load. Support for both polling mode and interrupt mode. Configurable Rx/Tx polarity. This allows using both inverting and non-inverting DALI bus drivers. Requirements Library is designed for the LPC11E37H and the LPC11U37H. Requires 1.5kB Flash storage. Counter/timer module CT16B1 is used by IOH and is no longer available to the ARM core. Pinning DALI Function Description Pin TxD DALI transmit data output PIO1_6/IOH_16 RxD DALI receive data input PIO1_7/IOH_17 I2S master The I/O Handler I2S library allows emulation of a basic I2S master (transmit only). I2S (Inter-IC Sound) is an electrical serial bus interface standard used for connecting digital audio devices together. It is used to communicate PCM audio data between integrated circuits in an electronic device. The IOH library allows emulation of a basic I2S master while not loading the CPU heavily with this task. The required CPU activity for this task is limited to ensure the data is available in the buffer in time for IOH to read it.After configuring and starting the I2S emulation, the I/O Handler continuously reads a 1kB data buffer and transmitting this buffer over the emulated I2S interface. After reading/transmitting the entire buffer, it wraps-around and begins reading/transmitting from the top of the buffer, thereby creating a continuous stream of data. An interrupt is asserted every time when the first half of the buffer has been read, and when the second half of the buffer has been read. This allows the CPU to fill the half of the buffer which is not being accessed by IOH with new data. Specifications Master mode only. Configurable for either I2S transmit or receive functionality (simultaneous transmit/receive not supported). 2 channels, 16-bit per channel. Loops over a 1kB data array. Requirements Library is designed for the LPC11E37H and the LPC11U37H. Requires 1kB Flash storage. Requires usage of one of any of the available timer modules (CT16B0, CT16B1, CT32B0 or CT32B1). Selected timer module is no longer available to the ARM core. Pinning I2S Function Description Pin SCL I2S bit-clock Any external match output pin of the selected timer (e.g. CT16B1_MAT0, CT32B0_MAT3, etc) WS I2S word-select output Configurable, following pins can be selected: IOH[7:0] TX_SDA I2S data output Configurable, following pins can be selected: IOH[7:0] RX_SDA I2S data input Configurable, following pins can be selected: PIO1_5/IOH_15 or PIO1_6/IOH_19 SCL_In I2S bit-clock input (requires to be connected externally to the SCL signal) Configurable, following pins can be selected: PIO0_8/IOH_6,  PIO1_6/IOH_16 or PIO1_27/IOH_20   I2C master The I/O Handler I2C library provides functionality to emulate an I2C master using the I/O Handler hardware block. The I2C bus was designed by Philips in the early ‘80s to allow easy communication between components which reside on the same circuit board. The IOH library allows I2C communication fully handled by IOH, with zero CPU load after a transfer has been initiated. The easy-to-use API is non-blocking and only passes the data to be transmitted to the I/O Handler.After a transfer has been initiated, the I/O Handler handles the full I2C transfer with zero CPU-load. The IOH interrupt is asserted when a transfer has been completed. The API supports functions like I2C write, I2C read and I2C read/write. Specifications Master mode only. Repeated start supported. Clock stretching supported. Bit rate up to 300Kbps for 48MHz CPU clock. Support for both polling mode and interrupt mode. Multi-master not supported. 10-bit address not supported. Requirements Library is designed for the LPC11E37H and the LPC11U37H. Requires 1.5kB Flash storage. Counter/timer module CT16B1 is used by IOH and is no longer available to the ARM core. Pinning I2C Functions Description Pin SDA I2C data input/output Configurable, following pins can be selected: PIO1_[31:0] SCL I2C clock output Configurable, following pins can be selected: PIO1_[31:0]     UART The I/O Handler UART library provides functionality to emulate a UART using the I/O Handler hardware block. The implemented UART is capable of full-duplex communication at common UART formats (7/8 databits, 1/2 stopbits), and with a configurable baud rate (up to 115200 baud). Flow control through hardware handshaking is supported (RTS/CTS). Receive and transmit FIFOs are configurable, and interrupts are generated based on FIFO thresholds. A low-level API offers receive and transmit primitives, as well as interrupt events. A sample driver demonstrates how to use this to create buffered I/O. Specifications Asynchronous, full-duplex. Baud rates up to 115200 for 48 MHz CPU clock. Data formats 7N1, 7N2, 8N1, 8N2. Hardware handshaking: CTS controlled by I/O Handler, RTS controlled by driver software. Requirements Library is designed for the LPC11E37H and the LPC11U37H. Requires 1.25 KiB Flash storage. Counter/timer module CT16B1 is used by IOH and is no longer available to the ARM core. Pinning UART Function Description Pin TXD UART transmit data output Freely selectable from the 21 possible I/O Handler pins IOH_0…IOH_20 RXD UART receive data input Can be selected from the following three pins: PIO0_8/IOH_6, PIO1_6/IOH_16, PIO1_27/IOH_20 CTS UART clear-to-send input Freely selectable from the 21 possible I/O Handler pins IOH_0…IOH_20. This signal is optional.   CRC The I/O Handler CRC library enables the I/O Hander hardware block as a CRC engine. A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage device to detect accidental changes to raw data. The IOH library allows CRC calculation to be performed by the I/O Handler peripheral with zero CPU load. Through the easy-to-use, non-blocking API of the library the emulated CRC engine can be configured, started and stopped.After a CRC calculation has been initiated, the IOH calculates the CRC over the raw data block with zero CPU load. When the calculation has finished, the IOH interrupt is asserted and the result of the calculation can be read through an API call. Specifications Supported polynomials: CRC-16-CCITT (x16 + x12 + x5 + 1) CRC-16-IBM (x16 + x15 + x2 + 1) Big endian and little endian data supported. Configurable seed. Support for both polling mode and interrupt mode. Requirements Library is designed for the LPC11E37H and the LPC11U37H. Requires 1kB Flash storage. Windowed Comparator The IOH windowed comparator allows monitoring up to 4 analog channels with zero CPU load. The ADC continuously converts all enabled channels, while IOH compares the converted values against a per-channel configurable window (consisting of an upper-limit and a lower-limit). When the converted value of any of the enabled channels is outside this window, an interrupt is generated. This task is fully handled by IOH at zero CPU load, meaning that in the meantime the ARM core can be put in sleep mode or execute other tasks. This provides a way to either lower the power consumption (ARM in sleep mode), or enhance performance (ARM executing other tasks). Specifications Converts up to all 8 available analog channels. Channel 0-3 can be selected for windowed comparator function. Interrupt is generated whenever any of the enabled comparator channels exceeds their window. True zero CPU-load. Requirements Library is designed for the LPC11E37H and the LPC11U37H. Requires 1.8kB Flash storage. ADC module is used by IOH and is no longer available to the ARM core. Note: Conversion result of enabled ADC channels available through API.

To build a project for IAR, select the Workspace file (eww) file for the example you want to build and deploy. The project will open up in the IAR EWARM IDE. For the project, select the build variant you want to build. Press F7 to build the selected project. Each project will generate a hex file in addition to the executable. Locate the hex file and use Flash Magic to program it into the board's FLASH. Before programming, make sure the board/devie is in ISP mode by holding down the SW6 button while pressing and releasing the reset button.

To use SWIM in Linux, SWIM must have direct access to the frame buffer memory in Linux. This can be done by accessing the /dev/fb device and mapping virtual memory to the device that SWMO will be used. The basic code snippet below shows how to do it. #define XSIZE 240 #define YSIZE 320 int fbdev; Uint16 *fb; /* Assumes frame buffer is 16-bit data */ /* Open frame buffer device */ fbdev = open("/dev/fb0", O_RDWR); /* Get mmap'd pointer to frame buffer */ fb = (Uint16 *) mmap(0, XSIZE * YSIZE * sizeof(Uint16), PROT_WRITE, MAP_SHARED, fbdev, 0); After this code is executed, the variable 'fb' will point to a usable frame buffer in memory that can be directly written to and read from in the Linux application. The next step is to initialize the SWIM window for the size of the display. SWIM_WINDOW_T win1; /* Create window with black background and no border */ if (swim_window_open(&win1, XSIZE, YSIZE, fb, 0, 0, XSIZE - 1, YSIZE - 1, 0, WHITE, BLACK, WHITE) == 0) { fprintf(stderr, "Error opening chat window\n"); close (fbdev); return -1; } /* select the font to use */ swim_set_font(&win1, (FONT_T *)&font_winfreesys14x16 ); /* set the pen color to use */ swim_set_pen_color(&win1, WHITE); A title bar can be easily added to the window. swim_set_title(&s1, "SWIM window demo", LIGHTGRAY); All objects in the window are drawn using logical window coordinates. Positions for pixels/lines and text are independent of each other, so you can draw some text, then do a line, and then if you draw text again, it will place the next where the previous text output ended before the line was drawn. /* Draw a simple box */ swim_put_line(&win1, 10, 10, 50, 10); swim_put_line(&win1, 50, 10, 50, 50); swim_put_line(&win1, 50, 50, 10, 50); swim_put_line(&win1, 10, 50, 10, 10); With Linux, finish the application by closing the frame buffer device. close (fbdev); The SWIM library and application note can be found here.

If you accidentally erase the kickstart or S1L boot loaders on the Embedded Artists LPC3250 board, this procedure can be used to restore them. Note the boot loaders provided in this restoration method might be newer than the versions provided with the Embedded Artists board. The original versions of the boot loaders can also be downloaded from the Embedded Artists 's website when you register your board.   Restoration of the boot loaders on the board require no special hardware (ie, JTAG) and are performed with boot loaders and tools built or included in the LPC32x0 Common Driver Library. However, you will need a PC with a USB port to perform the update procedure.   Restoring the kickstart loader and is a 2-step process. The kickstart loader is restored first and then is restored. The serial loader is used to transfer the application and the burner images (which is used to program the application into NAND FLASH). The LPC32x0 will automatically burn the image into NAND FLASH after it has been downloaded and then provide a status.   Step 1: Download the pre-built boot software and restoration images for the Embedded Artists LPC3250 board from the Resources page. Step 2: Extract the files on a Windows based PC Step 3: Connect a USB cable between the Embedded Artists boards USB serial connector and the PC. Power up the board and install and USB serial drivers if necessary. These drivers are included with the software included with the board. Step 4: Start the Serial loader software (LPC3250_Loader.exe) included in the pre-built boot software package. Step 5: Setup the 'Primary boot (IRAM)' file in the Serial loader to the burner_kickstart_nand_large_block_rvw.bin file. Setup the 'Secondary Executable (SDRAM)' file in the Serial loader to the kickstart_nand_large_block_rvw.bin file. Verify that the Comport control selection matches the COM part on the PC that is connected to the Embedded Artists board.   NOTE: The pre-built binaries may have slightly different names than those listed in steps 5 and 7, depending on the tool used to build the binaries. If the binaries were build with GNU instead of Realview, the 'rvw' field in each name will contain the 'gnu' identified instead. Change the filenames as necessary for you binaries you have.   Step 6: Press the 'Load bin's / Start primary' button on the Serial loader and power on the board. The burner image and the kickstart loader image should transfer to the board and the kickstart loader will then be programmed into NAND FLASH block 0 for boot from the boot ROM by the burner application. After the files have transferred, press the 'Enable terminal mode' button to see the program status. In the Status / Terminal output window of the Serial loader tool, you should see the following output. Waiting for BootID .. 5 .. found! Sending 'A' .. done! Expect 2-nd BootId .. 5 .. found! Sending 'U','3'.. done! Expect 'R' .. R .. found! Sending startaddress .. done! Sending size .. done! Sending code .. done! --- Loading Secondary executable --- Wait for 'X' .. X .. found! -- Sending command .. p ..done! Sending startaddress .. done! Sending size .. done! Wait for acceptance from primary boot .. o ..OK! Sending code .. done! Expect final 't' .. t .. found, ---- Secondary Executable loaded. --- --- Enabling terminal mode --- Formatting blocks... Format complete Writting kickstart into flash... Verifing data......Successfully NAND flash is programmed Successfully     Step 7: Setup the 'Primary boot (IRAM)' file in the Serial loader to the burner_s1app_nand_large_block_rvw.bin file. Setup the 'Secondary Executable (SDRAM)' file in the Serial loader to the s1l_from_kick_rvw.bin file. Verify that the Comport control selection matches the COM part on the PC that is connected to the Embedded Artists board.   Step 8: Press the 'Load bin's / Start primary' button on the Serial loader and reset the board. The burner image and the image should transfer to the board and will then be programmed into NAND FLASH block 1 (and on) for boot from the kickstart loader. After the files have transferred, press the 'Enable terminal mode' button to see the program status. In the Status Terminal output window of the Serial loader tool, you should see the following output.     Waiting for BootID .. 5 .. found! Sending 'A' .. done! Expect 2-nd BootId .. 5 .. found! Sending 'U','3'.. done! Expect 'R' .. R .. found! Sending startaddress .. done! Sending size .. done! Sending code .. done! --- Loading Secondary executable --- Wait for 'X' .. X .. found! -- Sending command .. p ..done! Sending startaddress .. done! Sending size .. done! Wait for acceptance from primary boot .. o ..OK! Sending code .. done! Expect final 't' .. t .. found, ---- Secondary Executable loaded. --- --- Enabling terminal mode --- Formatting blocks... Format complete Writting S1 image into flash... NAND flash is programmed Successfully Step 8: Close the Serial loader and open a terminal program, then reset the board Close the serial loader tool and open a terminal program such as Teraterm. Reset the board and should start. 5 Embedded Artist 3250 Board Build date: May 21 2010 15:12:06 Autoboot in progress, press any key to stop ea3250 >

This section explains how to use the MLC extractor tool to get an image with interleaved MLC data from NAND FLASH. The MET runs on the target hardware, so the image to be extracted must be placed on the hardware first. There are detailed swrites in the CDL on how to do this, so this won't be covered here. The program assumes UART 5 (the LPC32x0 boot UART) is used as the UART interface. The most common code extracted with this is the kickstart loader in block 0. This loaded is used to boot the LPC32x0 from NAND, setup the system, and then bootstrap the secondary loader in NAND blocks 1 and on. This example is shown on the Phytex LPC3250 board, although ti will work similar on other boards. Setup the serial loader tool to load the "mlcextractor.bin" file to the board via the serial port. M<ake sure the ServiceN pin on the LPC3250 is pulled low to enable UART boot mode. Press the "Load bin's/Start primary" button on the serial loader dialog window. Reset the board and the serial loader tool will transfer the MLC extractor to the target board. After the image is loaded, you will see a messaeg displaying the number of blocks and pages per block in NAND. If a message appears that says the NAND device coudn't be found, then the image needs to be rebuilt with the NAND IDs that match the NAND device on the target board. Close the serial load tool and open a terminal program that supports XMODEM transfer (ie, Teraterm). Press the space bar to get the MET menu. Pressing the keys defined by the menu allows you to change the starting block and number of blocks to extract the data for. Once they are selected, press 'd' and then 'y' to start the xmodem transfer. Next, setup the terminal program for an XMODE_cChecksum receive session. Once started, the interleaved data and ECC codes will be read from the NAND device and transferred to the file via XMODEM. This resulting file can be used for NAND programming.

Description This example implements a HID class device with mouse report descriptors. Key character reports are sent to the host by the device when buttons are pressed or the joystick is moved on the development board. Compiler build configurations The software that makes up this example is designed to run on many different development boards. Therefore the compiler must be configured to build an image that is targeted to the development board you are using. This section explains how to set these build configurations for each of the supported compilers.   LPCXpresso IDE Configure projects   right click on the BSP project in the project explorer window   click Build Configurations->Set Active->(see configuration in table below)   repeat these steps with the CDL, nxpUSBlib, and Example_KeyboardDevice Configure MCU   right click on the Example_KeyboardDevice project in the project explorer window   click Properties->C/C++ Build->MCU settings->(see configuration in table below) Configure the indexer    click Window->Preferences->C/C++->Indexer->Use active build configuration BSP CDL nxpUSBlib Example_KeyboardDevice MCU LPC1850  / Hitex LPC18xx_HITEX LPC18xx LPC18xx_Device LPC18xx LPC1850 LPC4330  / Xplorer LPC4330_Xplorer LPC18xx LPC18xx_Device LPC18xx LPC4330 LPC4350  / Element14 LPC1435_ELEMENT14 LPC18xx LPC18xx_Device LPC18xx LPC4350 LPC11U14 / LPCXpresso LPC11Uxx_LPCXpressoRevB LPC11Uxx LPC11Uxx_Device LPC11Uxx LPC11U14 LPC11U14 / MCB1000 LPC11u14_MCB1000 LPC11Uxx LPC11Uxx_Device LPC11Uxx LPC11U14 LPC1768  / MCB1700 LPC1768_MCB1700 LPC17xx LPC17xx_Device LPC17xx LPC1768 LPC1768  / LPCXpresso LPC17xx_LPCXpressoRevB LPC17xx LPC17xx_Device LPC17xx LPC1768 NOTE: The LPC18xx CDL is used with boards that hold LPC43xx parts. This is done because the LPC43xx CDL is currently experimental. The LPC18xx USB library is used because both parts share the same controller.   Keil uVision 4 IDE Configure a Batch Build     click on Project->Batch Build...   expand the BSP project to display a list of project targets   select the project target by checking the appropriate checkbox (see target list in table below)   repeat these steps with the CDL, nxpUSBlib_Device, and Example_KeyboardDevice BSP CDL nxpUSBlib_Device Example_KeyboardDevice LPC1850  / Hitex HITEX1800 LPC18xx LPC18xx_Device HITEX1800 LPC1768  / MCB1700 MCB1700 LPC17xx LPC17xx_Device MCB1700 LPC11U14 / MCB1000 MCB1000 LPC11Uxx LPC11Uxx_Device MCB1000   Board connections and configurations   LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  older A2 design schematic ./BSP/schematics/HITEX_SCM_LPC1850EVA-A2-2.pdf   Connect the JTAG to the 20 pin receptacle marked X4 JTAG Connect the type-B end of a USB cable to the receptacle marked X2. Plug the type-A end of this cable into a PC LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  newer A4 design schematic ./BSP/schematics/HITEX_Final_LPC1850EVA-A3.pdf   LPC4330_Xplorer (NGX Xplorer Evaluation Board with LPC4330) Connect the JTAG to the 10 pin receptacle marked J2 Connect the micro-b end of a USB cable to the receptacle marked USB0. Plug the type-A end of this cable into a PC   LPC1435_ELEMENT14 (Element 14 gaming board with LPC4350) Connect the JTAG to the 10 pin receptacle marked J6 Connect one end of a type-A to type-A USB cable to the receptacle marked USB0. Plug the other end of this cable into a PC   LPC11u14_MCB1000 (Keil MCB1000 development board) schematic: ./BSP/schematics/mcb1000-schematics.pdf   Jumpers:   J4 = 2-3      (UCON - PIO0_6 pulls D+ high)   J2 = 1-2          (VDD  - core power)   J5 not installed  (ISP  - ISP via COMM)   J6 not installed  (RST  - ISP via COMM) Connect the JTAG debugger to the 10 pin Cortex Debug connector labeled J3 Connect the type-B end of a USB cable to the type-B recepticle and the type-A end of the cable to the USB receptacle on a PC Once the USB cable is connected to the board the following LEDs should be illuminated:     Power     All 8 LEDs in PIO2   LPC1768_MCB1700 (Keil MCB1700 development board) schematic: ./BSP/schematics/mcb1700-schematics.pdf   Jumpers:   E/U    = 1-2  (Ethernet/USB)   UMODE  = 1-2  (USB Device Mode)   D-     = Device   D+     = Device   VBUS   = 1-2   VDDIO  = 1-2   VDDREG = 1-2   Connect the JTAG debugger to the 20 pin JTAG or 10 pin Cortex Debug connector. Connect the type-B end of a USB cable to the type-B recepticle labeled 'Device' and the type-A end of the cable to the USB receptacle on a PC. Once the USB cable is connected to the board the following LEDs should be illuminated:     Power     100MHz     USC (LED indicates a USB soft connect from P2.9)    LPC11Uxx_LPCXpressoRevB (LPCXpresso LPC11Uxx on the LPCXpresso Rev B base board) schematic: ./BSP/schematics/lpcxpresso.lpc11u14.schematic.pdf   Running this example on the LPCXpresso LPC11U14 can be done one of two ways:   1. LPCXpresso LPC11U14 stand-alone       Connect the type-B end of a USB cable to the mini receptacle on the LPCXpresso board labeled J8 and the type-A end to the USB receptacle on a PC   2. LPCXpresso LPC11U14 plugged into the LPCXpresso base board Rev B       Plug the LPCXpresso LPC11U14 board into the connector labeled J4 on a LPCXpresso base board Rev B       Configure the base board according to the user's guide from Embedded Artists       Connect the mini type-B end of a USB cable to the receptacle on the base board labeled X1 and the type-A end to the USB receptacle on a PC       Once the USB cable is connected to the board the following LEDs should be illuminated:           LED25  (vbus)          LED26  (3.3v rail)         For both configurations the JTAG debugger is connected to the mini USB receptacle labeled J3 on the LPCXpresso LPC11U14 board   LPC17xx_LPCXpressoRevB (LPCXpresso LPC17xx on the LPCXpresso Rev B base board) schematic: ./BSP/schematics/LPCXpressoLPC1769revB.pdf   Running this example on the LPCXpresso LPC1769 can be done one of two ways:   1. LPCXpresso LPC1769 stand-alone. Solder a type-B USB receptacle onto the board and wire it up. See included schematics for details. Connect the type-B end of a USB cable to the receptacle on the LPCXpresso board and the type-A end to the USB receptacle on a PC   2. LPCXpresso LPC1769 plugged into the LPCXpresso base board Rev B. Plug the LPCXpresso LPC1769 board into the connector labeled J4 on a LPCXpresso base board Rev B. Configure the base board according to the users guide from Embedded Artists. Connect the mini type-B end of a USB cable to the receptacle on the base board labeled X1 and the type-A end to the USB receptacle on a PC.    Once the USB cable is connected to the board the following LEDs should be illuminated:       LED25  (vbus)       LED26  (3.3v rail)         For both configurations the JTAG debugger is connected to the mini USB receptacle labeled J3 on the LPCXpresso LPC1769 board.   PC configuration Use a PC running Windows XP, Vista or 7 Connect the type-A end of the USB cable that is connected to the board into one of the USB receptacles on the PC Build and debug the example LPCXpresso IDE In the project explorer window of the IDE right click on the Example_KeyboardDevice project and select Debug As->C/C++ MCU Application In the main window of the IDE click Run->Resume to start running the application   Keil uVision 4 IDE In the Batch Build window, select the project targets as described in Compiler Build Configurations and then click Build In the main window of the IDE click Debug->Start/Stop Debug Session click Debug->Run   How this example runs and what to look for When the example is run and the board is connected to a PC with a USB cable it will enumerate on the PC as a HID Keyboard device. You should see the device appear in the "Device Manager" under "Keyboards". If you right click on HID Keyboard Device->Properties a window will appear called "HID Keyboard Device Properties". If you select the "Details" tab you will see a "Properties" drop down, click on it and select "Hardware Ids". You should see the below entries for Vendor Id and Product Id.   HID\VID_1FC9&PID_2042&REV_0001 HID\VID_1FC9&PID_2042   This information should match the data in the "Device Descriptor Structure" in the "Descriptors.c" file in the Example_KeyboardDevice project directory.   To demostrate the keyboard open an editing application such as Notepad or MS Word. Moving the joystick (SW2) on the Xpresso base board will output characters onto the editing application.

The NXP motor control library (nxpMClib) supports various types of motor control for the Cortex-M family. Built on CMSIS2.0 math and DSPLIB. Supported by motor control GUI with selection for each supported type. Includes real time data view comm library. Currently available examples: lpc18xx/43xx FOC dual shunt Watch this Video of the FOC implementation: Video Field Oriented Control on the NXP LPC1800 Microcontroller Library layers The motor control library is separated in four layers. The bottom layer contains the peripheral drivers. On top of the driver layer is a generic collection of control algorithms to drive the peripherals. On top of that resides the layer that defines the motor control type and contains the state machines to drive the specific type. Finally there is the application layer that determines the interfaces to the library and initializes the application specific motor control type, peripheral setup and interconnection. Download Get the latest software package including the library, example code, the tool installer and documentation attached.

If you already have S1L on your FDI board, you can update to a previous or later version of S1L with the following procedure. This procedure should not be used to update the kickstart loader in block 0. Step 1: Boot the system to the S1L prompt. Have your updated version of S1L ready. Step 2: At the S1L prompt, type 'load term raw 0x90000000' to start the binary receive in S1L of the new image. On your terminal program, send the S1L file (ie, s1l_from_kick_gnu.bin) to the board as a binary file. Step 3: Once transfer completes, send a break to the board to return to the prompt. In TeraTerm, a break can be sent from the Control menu or by pressing ALT-B. Step 4: Erase the blocks in FLASH used for S1L storage. These are blocks 1 to 24. Be very careful not to erase block 0, which is used for the klickstart loader. The 'erase 1 24' command can be used to erase the blocks. Step 5: Write the loaded S1L image into the S1L area starting at block 1. The S1L image is usually between 56K and 80K, so it will easily fit in 1 block. The command 'write 0x90000000 64 64' will perform this operation. The write command take sectors (not blocks) - sector 64 is where block 1 starts. Step 6: Reset the board to verify the S1L image has been updated. The entire sequence is shown below. You can see a different version of S1L is running by examining the build date of S1L when it boots. FDI3250 Kickstart v1.00 NAND Flash Initialized Running Stage 1 Loader ... Future Designs, Inc. DK-xTS-LPC3250 Board Build date: Sep 10 2010 10:12:22 Autoboot in progress, press any key to stop linux>load term raw 0x90000000 Starting terminal download, send break to stop File loaded successfully linux>erase 1 24 Operation will overwrite bootloader - ok?(y/n): Starting block erase linux>write 0x90000000 64 64 linux>FDI3250 Kickstart v1.00 NAND Flash Initialized Running Stage 1 Loader ... Using default system configuration Future Designs, Inc. DK-xTS-LPC3250 Board Build date: Sep 13 2010 11:20:12 FDI3250

A block diagram of the dual core IRAM demo is shown below. Per the diagram, FreeRTOS runs on both cores with memory for the M4 core in the first 64K of IRAM. The M0 core uses the 32K of IRAM at offset 64K. The M0 and M4 signal each other via the core interrupt event mechanism. IRAM at address 0x10080000 is used for the shared memory queue. The tri-color LED is used to indicate lfe on a specific core. The red LED will blink when the M4 core is running, while the blue LED will blink when the M0 core is running. The green LED will blink at a varying rate when the M0 core is running and data has been supplied in the shared memory queue from the M4 core.

This is the uCOSIII port for LPC43XX based hitex board with revision A4. The BSP and the applicaton code for the port is attached below. The tools supported to build the package are: a) Keil uVision. It has been tested with V4.53.0.0 There are three attachments on the page containing i)The BSP,application and the CPU port files. ii)OS port for the core. iii) A png file showing the directory structure of the project. Here is a set of instructions to build and test the port: 1) Unzip the uCOSIII_Port.zip attachment and you should have "EvalBoards" and "uC-CPU" folders.Place them in your convinient folder. 2) Download uCOSIII source from http://micrium.com/page/downloads/download_os-III_source_code 3)You should now have a "Source" folder containing uCOSIII sources. Place this folder in The directory structure should look like the one shown in the attached png file. 4)Now, find the project file at 5)Double click "hitex4350_tcpecho_uCOSIII.uvproj" which opens the project. Go ahead and build the project for the required target. 6) Connect the Target "Hitex board" with J-Link. And Power it ON. You can either power it with USB or external supply. The default project is setup to use JLink. 7) You can download the image to the IRAM or flash depending on the target you have built. 😎 Run the image, you should be able to ping and telnet it.( This project uses static IP, so change your IP according to your need in the main.c file before building the image)

Description This example implements a HID class host mode device that enumerates a HID class device with keyboard report descriptors and displays key press characters on a terminal. NOTE: many keyboards enumerate as a HUB device which is not supported by this example. Compiler build configurations The software that makes up this example is designed to run on many different development boards. Therefore the compiler must be configured to build an image that is targeted to the development board you are using. This section explains how to set these build configurations for each of the supported compilers.   LPCXpresso IDE Configure projects   right click on the BSP project in the project explorer window   click Build Configurations->Set Active->(see configuration in table below)   repeat these steps with the CDL, nxpUSBlib, and Example_KeyboardHost Configure MCU   right click on the Example_KeyboardHost project in the project explorer window   click Properties->C/C++ Build->MCU settings->(see configuration in table below) Configure the indexer    click Window->Preferences->C/C++->Indexer->Use active build configuration   BSP CDL nxpUSBlib Example_KeyboardDevice MCU LPC1850  / Hitex LPC18xx_HITEX LPC18xx LPC18xx_Host LPC18xx LPC1850 LPC4330  / Xplorer LPC4330_Xplorer LPC18xx LPC18xx_Host LPC18xx LPC4330 LPC4350  / Element14 LPC1435_ELEMENT14 LPC18xx LPC18xx_Host LPC18xx LPC4350 LPC1768  / MCB1700 LPC1768_MCB1700 LPC17xx LPC17xx_Host LPC17xx LPC1768 LPC1768  / LPCXpresso LPC17xx_LPCXpressoRevB LPC17xx LPC17xx_Host LPC17xx LPC1768 NOTE: The LPC18xx CDL is used with boards that hold LPC43xx parts. This is done because the LPC43xx CDL is currently experimental. The LPC18xx USB library is used because both parts share the same controller. Keil uVision 4 IDE Configure a Batch Build     click on Project->Batch Build...   expand the BSP project to display a list of project targets   select the project target by checking the appropriate checkbox (see target list in table below)   repeat these steps with the CDL, nxpUSBlib_Host, and Example_KeyboardDevice BSP CDL nxpUSBlib_Host Example_KeyboardDevice LPC1850  / Hitex HITEX1800 LPC18xx LPC18xx_Host HITEX1800 LPC1768  / MCB1700 MCB1700 LPC17xx LPC17xx_Host MCB1700   Board connections and configurations LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  older A2 design schematic ./BSP/schematics/HITEX_SCM_LPC1850EVA-A2-2.pdf Connect the JTAG to the 20 pin receptacle marked X4 JTAG Connect a keyboard into the type A receptacle marked X10 Connect a 9-pin serial cable into the receptacle marked UART X1. Connect the other end of this cable into a PC running a terminal program. To power the board:   Connect the type-B end of a powered USB cable into the receptacle marked X13   or   Supply 5v to the DC connector labeled X14   LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  newer A3 design schematic ./BSP/schematics/HITEX_Final_LPC1850EVA-A3.pdf   LPC1768_MCB1700 (Keil MCB1700 development board) schematic: ./BSP/schematics/mcb1700-schematics.pdf Jumper Setting   E/U 1-2 UMODE 1-2 D- Host D+ Host VBUS 1-2 VDDIO 1-2 VDDREG 1-2 ISP removed Connect the JTAG debugger to the 20 pin JTAG or 10 pin Cortex Debug connector Connect a 9 pin serial cable between COM0 on the board and a PC running a terminal program. Baud rate = 9600 Plug a keyboard into the type A receptacle marked HOST To power the board:   Connect the type-B end of a powered USB cable to the type-B receptacle labeled 'Device'   or   Supply 5v to the -VIN+ pins between the JTAG and COM0 receptacles Once the board is powered the following LEDs should be illuminated:     Power     100MHz     USC   LPC17xx_LPCXpressoRevB (LPCXpresso LPC17xx on the LPCXpresso Rev B base board) schematic: ./BSP/schematics/LPCXpressoLPC1769revB.pdf   Plug the LPCXpresso LPC1769 board into the connector labeled J4 on a   LPCXpresso base board Connect the JTAG to the mini USB receptacle labeled J3 on the LPCXpresso LPC1769   board Configure the base board according to the users guide from Embedded Artists Install jumpers 1-2, 3-4, 5-6 on the jumper block marked J61 on the base board Plug a keyboard into the type A receptacle marked J60 on the base board Connect the mini type-B end of a USB cable to the USB-to-serial receptacle on   the base board labeled X3 and the type-A end to the USB receptacle on a PC. Once the USB cable is connected to the board the following LEDs should be   illuminated:     LED25  (vbus)     LED26  (3.3v rail)          PC configuration Use a PC running Windows XP, Vista or 7 to display runtime diagnostics that can be viewed with a terminal emulation program like Teraterm or Hyperterm. The baud rate in these programs should be set to 9600.   Build and debug the example LPCXpresso IDE In the project explorer window of the IDE right click on the Example_KeyboardHost project and select Debug As->C/C++ MCU Application In the main window of the IDE click Run->Resume to start running the application   Keil uVision 4 IDE In the Batch Build window, select the project targets as described in Compiler Build Configurations and then click Build In the main window of the IDE click Debug->Start/Stop Debug Session click Debug->Run   How this example runs and what to look for When the example is first run the terminal window will display: Keyboard Host Demo running.   When the keyboard is plugged in the terminal window will display: Device Attached. Keyboard Enumerated.   When a key is pressed on the keyboard an upper case character corresponding to that key will be displayed in the terminal window.   When the keyboard is unplugged the ternimal window will display: Device Unattached.

This section explains the LPC32x0 boot process for the various non-volatile memory types or the UART. Depending on the boot device, there may be limitations to the boot image size. This limitation may prevent a desired image from initially loading and executing – instead requiring a smaller boot loader to be loaded first and then using it to load and run a more capable boot loader or application. LPC32x0 boot options The LPC32x0 supports booting from small and large block NAND FLASH, SPI EEPROMS or FLASH, NOR FLASH, and via the UART. In production systems, the UART boot method isn't used. However, the UART boot method serves a useful purpose in early board debug, The boot order for the LPC32x0 is as follows: UART, SPI, NOR, NAND. UART boot can be disabled to reduce boot time. Each boot device will be tried prior to the next device. A device is bootable if the boot ROM locates a special boot pattern that identifies the device as bootable. It's possible that a system can have SPI FLASH, NOR FLASH, and NAND FLASH and only boot from NAND FLASH although the SPI and NOR methods are attempted first. (For example, the Phytec 3250 board has all 3 of these boot devices, but normally boots from NAND FLASH). When the LPC32x0 chip is reset, the internal boot ROM is executed. It queries each device looking for a special boot pattern used to identify the device as bootable. The first device that returns a correct pattern will be used by the boot ROM as the bootable device. The boot ROM will then either copy data from the bootable device (NAND and SPI FLASH) or transfer control to the bootable device (NOR FLASH). Each boot method is explained in the following sections. See the LPC32x0 User's guide for more information on the LPC32x0 boot process. UART boot The UART boot option allows a binary to be downloaded into the board and then executed prior to any code running in NAND, SPI, or NOR FLASH. This is useful for burning new images into FLASH, testing simple applications, or recovering the board from corrupt boot code. UART boot is used with the burner tools in the CDL package to program the bootloader(s) into the boot device. UART5 is supported with the UART boot option, so new designs should make UART5 available for debugging. For a system that entirely runs from IRAM, this allows a system to download an image via the UART that provides interactive access once the image is executed. The downloaded interactive program can be used for bandwidth or memory tests, register dumps, further image loading, or other functions. Initial versions of S1L can be used with this boot method to test different SDRAM configurations using the included SDRAM initialization code. Using this approach, startup and debug of the SDRAM code (one of the tougher issues of bringing up a new board) can be drastically simplified. NOR FLASH boot On a system that boots from NOR FLASH, the ARM core directly executes code from the NOR FLASH device starting at address 0xE0000004. The first 4 bytes at address 0xE0000000 are used for the special boot pattern value required by the boot ROM to identify the device as bootable and to provide the boot width (8, 16, or 32 bits). SPI FLASH/EEPROM boot On a system that boots from SPI, a small image is copied from the SPI EEPROM or FLASH device at offset 0x8 into IRAM at address 0x00000000. The first 4 bytes are used for the special boot pattern value required by the boot ROM. The next 4 bytes are used to designate the size of the image to load at offset 0x8 in the SPI device. After the image is loaded into IRAM, control is transferred to address 0x00000000. The maximum image boot size that can be loaded with this method is 54K. NAND FLASH boot On a system that boots from NAND FLASH, a small image is copied from block 0 or block 1 of the NAND device into IRAM at address 0x00000000. The maximum bootable image size for NAND FLASH boot is 54K, or 1 block minus 1 page, whichever is smaller. The first page of the boot block is used to store boot information, such as the boot image size and values needed by the boot ROM used for the boot sequence. For small block NAND (32 pages per block and 512 bytes per page) with the first page of the block dedicated to the boot ROM boot information, the maximum boot size is 31 pages of 512 bytes per page, or 15.5K. For large block NAND (64 pages of 2Kbytes per page), the maximum boot size is 54Kbytes. The boot ROM always uses the MLC NAND controller for NAND boot. This requires the boot image booted from NAND by the boot ROM to be programmed into NAND with the MLC NAND controller or with the ECC algorithms required by the MLC NAND controller.

CDL boot loader introduction The u-boot boot loader cannot be booted directly from the LPC32x0 boot ROM. Instead, a small loader program must be used to initialize the memory used by u-boot and then load it from it's non-volatile storage into memory before executing it. Because u-boot loads and executes from SDRAM, this initial loader must also initialize SDRAM. The CDL provides a reference boot loader called the kickstart loader that is meant to be the primary boot image loaded from the LPC3250 boot ROM. The kickstart loader can reside in NAND, NOR, or SPI FLASH and can be configured to load an image from any source into any address with any size. More information about the LPC32x0 boot process can be found on the LPC32x0 boot process page or in the LPC32x0 User's guide. The CDL has been ported to the Phytec, Embedded Artists, and Future Designs boards.   Kickstart loader and stage 1 definitions The terms kickstart loader and stage 1 application are used to describe the bootable images for the LPC32x0. A stage 1 application is the application we would ideally like to start when the LPC32x0 is reset or powered up. Stage 1 applications include programs such as u-boot, e-boot, or another full-featured application. Unfortunately, most stage 1 applications are too big to be directly booted by the LPC32x0 boot ROM. For systems where the stage 1 application can’t be directly booted, a smaller ‘kickstart’ boot loader is required to boot from the LPC32x0 boot ROM and then continue loading and start execution of the stage 1 application. For systems that boot from large block NAND FLASH or SPI FLASH, the maximum boot image size is 54K. If the application to be loaded exceeds this size or if the application needs to be loaded anywhere besides IRAM, the kickstart loader is required. The kickstart loader will in turn load the stage 1 application and transfer control to it after it has been loaded. If the application to be loaded is smaller than 54K and resides in IRAM, the stage 1 application can be directly loaded from the boot ROM instead of being routed through the kickstart loader. For systems that boot from small block NAND FLASH, the maximum boot image size is 15.5K. For systems that boot from NOR FLASH, no kickstart loader is needed (in most cases). The stage 1 application can be executed directly from NOR FLASH.   Kickstart loader The kickstart loader must be developed to be smaller than 54K (15.5K for systems that boot from small block NAND FLASH). This loader can include startup code that sets up the board’s initial GPIO states and muxes, setup the initial clocking, setup a basic MMU table if needed, setup all the memory interface, and then load an image and transfer control to that image. For small block NAND systems with the 15.5K boot image limit, this can be tough to manage. Tradeoffs may need to be made on what functions can be handled by the kickstart loader. Enabling all the functions may make a kickstart image that exceeds 15.5K. The image size would have to be reduced in this case by removing features from the kickstart loader and moving them to the stage 1 application. If your stage 1 application needs to execute in SDRAM, but the kickstart is too large with all the SDRAM init code, then code needs to be rearranged or aggressively optimized to meet the boot image size limitation.   Kickstart loader bootup procedure The following sequence shows how the LPC32x0 handles kickstart load and transfer from the boot ROM using NAND or SPI FLASH. LPC32x0 processor is reset LPC32x0 boot ROM interrogates boot devices For SPI FLASH, the image loaded at SPI FLASH offset 8 is loaded into IRAM at address 0x0 For NAND FLASH, the image loaded in page 1 of block 0 or 1 is loaded into IRAM at address 0x0 After the image is loaded, the boot ROM transfers control to the image’s startup code loaded at address 0x0   Stage 1 applications Stage 1 applications are applications that meet one of the following criteria: Loads and executes directly from the UART into IRAM Loads and executes from the kickstart loader in IRAM or SDRAM Loads and executes in place from NOR FLASH For Linux, u-boot can be considered a stage 1 application. For the Phytec and Embedded Artists boards, the kickstart loader loads S1L as the stage 1 application. S1L initializes the board functions such as clocking and SDRAM and then loads and starts u-boot. Optionally, the kickstart loader can use u-boot as the stage 1 application bypassing S1L. Stage 1 Loader The Stage 1 Loader (S1L) is an optional stage 1 application that provides debug, monitor, and boot support for an NXP micro controller. It can be used as the initial boot image the micro controller executes and then configured to load another image automatically. S1L is included free as part of the LPC32x0 CDL and is pre-installed on the Embedded Artist and Phytec LPC3250 based development boards. It can also be installed on Future Design LPC3250 based boards.The main features of the stage 1 loader are shown below: Register and memory change and dump Poke, peek, dump, fill Image load via a serial port , SDMMC card, or FLASH Supports raw binary and S-record files Images can be executed after loading Images can be saved in NAND FLASH NAND FLASH support Erase of NAND blocks Direct read and write of FLASH blocks and pages Bad block management MMU functions Data and instruction cache control Virtual address translation enable/disable Virtual address remapping Page table dump System support functions Baud rate control, clock control, system information Automatic load and run support Automatic load and execution of images from NAND FLASH, SDMMC, or via the terminal Testing functions SDRAM memory tests, bandwidth tests SDRAM calibration and configuration data   Other features of the CDL This CDL provides a generic set of drivers which highlight how specific peripherals and functions work. The CDL also provides Board Support Packages (BSP) for development boards based on the LPC32x0 microcontrollers. The BSPs provide reference code for system startup including boot loaders, system clock setup, SDRAM setup, and MMU/cache setup.The CDL provides the following features: Various drivers and header files for the LPC32x0 microcontroller Common software and definitions for LPC32x0 microcontrollers Support for Keil uVision4, ARM Realview 3.1, and GNU CodeSourcery tool chains BSPs for Embedded Artists, Phytec, and Future Designs LPC3250 based development boards A reference BSP for the NXP LPC32x0 based validation and reference platform A generic BSP that contains universal startup code for easy porting to a new LPC32x0 based platform Free for use with NXP LPC32x0 microcontrollers The Phytec, Embedded Artists, and Future Designs LPC3250 BSPs provide the following features: Startup code and board initialization code based on the board’s possible boot modes and devices Software to re-burn the boot loaders into NAND, SPI, or NOR FLASH Updated versions of the kickstart loader and S1L applications Tool-less software deployment options when used with the Stage 1 Loader or the Serial Loader Various peripheral examples that can downloaded and executed via S1L or a debugger Quickstart instructions The NXP LPC32x0 validation and reference platform is not commercially available, although the code included in the BSP is provided as part of the CDL. A generic LPC32x0 BSP is also provided as part of this CDL. This generic BSP provides the following features: Configurable startup code and board initialization code Standard and mobile single and double data rate SDRAM reference code based on the JEDEC SDRAM initialization sequence Reference drivers for small and large block NAND FLASH using the MLC and SLC controllers SPI FLASH and NOR FLASH reference drivers Burner software for burning and updating images in NAND, SPI, or NOR FLASH Various kickstart loader and S1L examples for multiple deployment methods Ideal for new board bringup (support for IRAM only boot via the Serial loader tool) Documentation that explains the reasoning and structure of the software