Content originally posted in LPCWare by IanJames on Tue Jun 25 06:55:16 MST 2013
This is what I have found so far..........
I configure the Watchdog for Chip Reset thus:
LPC_SYSCON->WDTOSCCTRL = 0x003F; // 001 11111 ~8kHz
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<15); // Enable clock to WDT
LPC_SYSCON->PDRUNCFG &= ~(0x1<<6);// ensure watchdog is powered
LPC_WWDT->CLKSEL = 0x01;// Watchdog Oscillator as source 0001
LPC_WWDT->WARNINT = 0x00;// Interrupt warning value
NVIC_EnableIRQ(WDT_IRQn);// Enable the interrupt
LPC_WWDT->TC = 0xFF; // once WDEN is set, the
LPC_WWDT->MOD = 0x0003; // start in Chip Reset Mode
__disable_irq();
LPC_WWDT->FEED = 0xAA;/* Feeding sequence */
LPC_WWDT->FEED = 0x55;
__enable_irq();
/* Make sure feed sequence executed properly */
for (i = 0; i < 0x80000; i++);
If I compile for Release mode, Program over the SWD, power off remove programmer and power on then everything appears to work correctly i.e. if I feed the watchdog at regular intervals then the processor runs if I disable feeding then the processor resets.
If I compile for Debug mode and repeat the above then after cycling the power then the processor appears to be in an unknown state - I know this because opon power up a single byte should be transmitted out of the serial port but nothing appears.
The only way to recover is to reprogram the chip.
Any thoughts anyone?
One other point, the manual suggests that if the processor is reset due to a Watchdog Reset then the bit 2 in the LPC_WWDT->MOD register should be set, but it doesn't appear to be.
**** Update ****
The register LPC_SYSCON->SYSRESSTAT contains the reset information [POR,EXT,WDT,BOD,SYS]