UART Shift Register Empty Interrupt

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UART Shift Register Empty Interrupt

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by John Sinclair on Sun Jul 29 23:59:24 MST 2012
Hello,

I have to develop a RS485 Master. So I have checked the Uart_Rs485Master Projekt on LPCware. This was good to start, the only messy thing is: When I have to send an address byte, I have to stick the parity on this byte and have to wait until the TX Shift Register (UnTSR) is empty. This was done in a while loop polling the LSR->TEMT flag.
Instead polling is there a chance to get an interrupt after the adress-byte was send?
Thx
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by jdurand on Mon Aug 06 08:56:17 MST 2012
There are a few things with UARTs that catch people:

1) What do you do in the TX interrupt when the last bite has already been sent?

2) How do you get the TX interrupted started again when there's more data to send?

3) If you have a half-duplex system or have to send a BREAK between frames, how do you know when the last byte has left the UART so you don't clip it off with the BREAK or direction change?


One way I've solved #1 & #2 above using the OS timer tick (typically 10mS) (solution depends on the system).  In case #1 when there's no more data to send the interrupt sets a UART_IDLE flag and returns from the interrupt.  In the OS timer tick hook I check the idle flag and if set and there's data available, I generate a UART TX interrupt to restart the transmission.

For systems with BREAK I usually have a timer running since the frames often have to go out at a set rate.

A sometimes harder thing to deal with is having a receive buffer while allowing the user to backspace.  I've used a single linear buffer and sometimes add a ring buffer between the UART and the linear one to allow faster transfers. This is easy to handle filling/backspacing and when a RETURN buffer parsing starts.  Not the most efficient but if dealing with a human typing it works quite well.  Handshaking to the host is controlled by either the start/end of parsing, the UART itself, or the ring buffer handler.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by SteveMerrick on Mon Aug 06 06:56:45 MST 2012
Your problem illustrates a shortcoming in the MCU's design. :-( Many firmware designers could do with an interrupt that becomes active when the final bit of the final byte has been clocked out of the transmit shift register. Unfortunately, there is no such interrupt. You may have to do what we did: dedicate [i.e. waste!] a counter-timer to time when the UART output is complete, and generate an interrupt. It makes me angry every time I think about it. ;-)
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by John Sinclair on Mon Jul 30 06:33:34 MST 2012
I have found a solution:
The Uart Fifo have a initialization conditions with a character delay in the interrupt. So you have write only one byte (the address byte) in the fifo with the parity stick bit set. Through the initialization condition the THRE interrupt will occur later and you can clear the parity stick bit without disrupt the first address byte.
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