SDRAM EMC_CLK2 with EMC_CKEOUT0 and EMC_DYCS0

[lpcware]

Content originally posted in LPCWare by wlamers on Fri May 31 02:20:40 MST 2013

Hello,

I have read on this forum that the CLK2 clock output for the EMC controller has better timing characteristics/margin. So I want to use it for a single SDRAM (Micron MT48LC16M16 A2P). Do I need to use the clock enable output EMC_CKEOUT2 and chip select EMC_DYCS2 also? Or can I use the CKEOUT0 and DYCS0 combined with the CLK2?

Note that the CLK0 pin is set to EMC_CLK01 and de CLK2 pin to EMC_CLK23 such that I have CLK1 pin available for CLKOUT (debugging purposes). CLK3 pin is not used at all.

[lpcware]

Content originally posted in LPCWare by DF9DQ on Tue Jun 04 02:33:11 MST 2013

There's no problem with your PCB. Using DYCS2/CKEOUT2 is perfectly valid!

If you measure the SDRAM timings, you will find the SDRAM setup timing (control signals stable prior to rising clock edge) is a bit hard to satisfy at higher frequencies. If the clock were delayed a little bit, you would have higher margin. The easiest way to get that delay is to use that clock signal out of EMC_CLK0...3/EMC_CLK01/EMC_CLK23 which (due to inevitably different paths on the chip) comes latest. This turns out to be EMC_CLK23 @ CLK2 pin (0.5 ns "better" than CLK0), and this is why this signal is the recommended clock!

[lpcware]

Content originally posted in LPCWare by wlamers on Mon Jun 03 09:11:28 MST 2013

Thank you for that information. It explains a lot!

Unfortunately I already have changed the PCB layout to using CLK23,, CKEOUT2 and DYCS2. With the clocks on CLK01 (pin CLK0) and CLK23 (pin CLK2, which also goes to SDRAM). But if I understand your explanation correctly this is no issue, other than having an other start adress of the SDRAM. Can you, or someone else, confirm this?

Can you explain what you mean with 'the largest SDRAM setup time' ? I cannot find information about this in the manual nor datasheet. I got that tip on using CLK2 from someone from NXP on this forum.

[lpcware]

Content originally posted in LPCWare by DF9DQ on Mon Jun 03 08:57:36 MST 2013

The four clock signals EMC_CLK0...EMC_CLK3 are not related to the four chip selects! They clock the four byte lanes (EMC_CLK0 = LSB, EMC_CLK3 = MSB) of a 32-bit word. All four clocks are needed, no matter what the external bus width is, or the CPU may stall on an external memory access.

EMC_CLK01 and EMC_CLK23 each combine two of these clocks, such that only two clock pins (CLK0 and CLK2) have to be used to get all four clocks, leaving CLK1 and CLK3 pins free for other purposes.

The clock signals are functionally identical, and can therefore be used in combination with whatever dynamic chip select you like (EMC_DYCSx). Note that the EMC_CKEOUTx signals belong to chip selects, not clocks. So in your case you can indeed use EMC_DYCS0+EMC_CKEOUT0 with clock EMC_CLK23 on pin CLK2!

The "better" electrical timing characteristic of EMC_CLK23 @ CLK2 refers to it offering the largest SDRAM setup time available of all clock signal / clock pin combinations.