Problem with NAND

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Problem with NAND

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NXP Employee
NXP Employee
Content originally posted in LPCWare by Ildar on Tue Feb 14 02:18:28 MST 2012
Hi! We create custom board with LPC1788 and NAND Flash (K9F5608U0D-PCBO). And we try to port u-boot on this board, but we have problems with NAND Flash. For example, we write data to flash, then read data, but we get only 0xFF. From difference we have only oscillator frequency and pins (CLE(Command LATCH Enable) and ALE(Address LATCH Enable)). Would somebody help us?
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NXP Employee
NXP Employee
Content originally posted in LPCWare by Ildar on Wed Mar 14 01:20:08 MST 2012
I was found one source of problem - in u_boot pin P4.31 was not settings up as GPIO but as NAND_CE. Is mistake of u_boot port makers and my because I did't see this error. Now data is write and read from NAND but with mistakes (21% approximately). Any body may known why? Thanks for any help!

Regards.
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NXP Employee
NXP Employee
Content originally posted in LPCWare by Ildar on Wed Feb 15 02:13:20 MST 2012
Attached file DiffPinsTable.jpg
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NXP Employee
NXP Employee
Content originally posted in LPCWare by Ildar on Tue Feb 14 23:38:20 MST 2012
Thanks you for replay! But I was did it, yet.
This is console output where CONFIG_MTD_DEBUG defined and CONFIG_MTD_DEBUG_VERBOSE defined as MTD_DEBUG_LEVEL3 (Noisy)

#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE MTD_DEBUG_LEVEL3

********************************************************************************************
U-Boot 2011.06 (Feb 15 2012 - 12:26:21)

NXP LPC1788 Cortex-M3
DRAM:  32 MiB
Flash: 512 KiB
NAND:  NAND device: Manufacturer ID: 0xec, Chip ID: 0x75 (Samsung NAND 32MiB 3,3V 8-bit)
32 MiB

Bad block table not found for chip 0
Bad block table not found for chip 0
Scanning device for bad blocks
nand_read_oob: from = 0x00000000, len = 16
nand_read_oob: from = 0x00000200, len = 16
nand_read_oob: from = 0x00004000, len = 16
nand_read_oob: from = 0x00004200, len = 16
...
********************************************************************************************

This is table of board differences for NAND:

_________________________________________________________________________________________________________________
Pin Name | Description          | Function | Pin Number in EA board | Pin Number in Custom board | Is_difference |
---------|----------------------|----------|------------------------|----------------------------|---------------|
RB       | Ready/Busy Output    | GPI      | P2.21                  | P2.11                      | YES           |
OE       | Read Enable          | EMC_OE   | P4.24                  | P4.24                      | NO            |
CE       | Chip Enable          | GPO      | P4.31                  | P4.31                      | NO            |
CLE      | Command LATCH Enable | EMC_A    | P4.20 (P4.21?)         | P4.18                      | YES           |
ALE      | Address LATCH Enable | EMC_A    | P4.19                  | P4.19                      | NO            |
WE       | Write Enable         | EMC_WE   | P4.25                  | P4.25                      | NO            |
WP       | Write Protect        | ?        | ?                      | 3.3 V                      | ?             |
DQ0      | P3.0                 | EMC_D[0] | P3.0 (?)               | P3.0                       | NO (?)        |
...      | ...                  | ...      | ...                    | ...                        | ...           |
DQ7      | P3.7                 | EMC_D[7] | P3.7 (?)               | P3.7                       | NO (?)        |
_________|______________________|__________|________________________|____________________________|_______________|

(Sorry, but table loose formatting in message, but I attached DiffPinsTable.jpg))

And that is I changed:

In nand.c:

// For EA board
//#define NAND_ALE_OFFS(1 << 19)
//#define NAND_CLE_OFFS(1 << 20)

// For Custom board
#define NAND_ALE_OFFS(1 << 19)
#define NAND_CLE_OFFS(1 << 18)


static int intmash_tscr_nand_device_ready(struct mtd_info *mtd)
{
/* If NAND doesn't work, check jumper JP2-3-4 on base board */
// For EA board
// return lpc17xx_gpio_get_state(2, 21);

// For Custom board
   return lpc17xx_gpio_get_state(2, 11);
}


/*
* Setup NAND timing and standard NAND functions
*/
int board_nand_init(struct nand_chip *nand)
{
/* Setup CS1 on p4.31 for GPIO output instead of CS1 */
lpc17xx_gpio_set_output(4, 31);
intmash_tscr_set_nand_cs(1);

/* P2.21 for NAND ready configured as GPIO input */
// For EA board
// lpc17xx_gpio_set_input(2, 21);

// For Custom board
   lpc17xx_gpio_set_input(2, 11);
...
}

In pins.c:

// For EA board
/* P2.11 (D) = LCD clock in */
2, 11, IOCON_D_TYPE,
.iocon.d = {
.func= 7,
.mode= LPC17_NO_PULLUP,
.hys= 0,
.inv= 0,
.slew= 0,
.od= 0
}

// For Custom board
/* P2.11 (D) = GPIO */
2, 11, IOCON_D_TYPE,
.iocon.d = {
.func= 0,
.mode= LPC17_NO_PULLUP,
.hys= 0,
.inv= 0,
.slew= 0,
.od= 0
}


Any ideas? What am I doing wrong?

Thanks,
Ildar
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NXP Employee
NXP Employee
Content originally posted in LPCWare by wellsk on Tue Feb 14 09:50:47 MST 2012
It could be a number of issues. Is NAND FLASH being correctly identified now in u-boot? Are you getting a message at u-boot startup specifying the size of FLASH similar to this?
>NAND:  128 MiB

If you did a custom board, I would check the status of the RDY/BUSY signal going to the chip and verify the lpc17xx driver is using the correct GPI to monitor this signal state? I would also verify that the offset values for the control (CLE) and address (ALE) to the external memory control are correct. You should also verify that the chip select is correct. All of these specific GPI/GPO/GPIO pins need to be muxed to the correct state and set in the correct direction.

The NAND driver is a board level driver and will need to be customized for your board. The driver source is here:
http://git.lpclinux.com/?p=uboot-2011.06-lpc17xx.git;a=blob;f=board/nxp/ea1788/nand.c;h=e0ebc7595fb8...

See the comment below in the driver about some info on setup. Note the EA1788 specific driver uses CS1 in GPIO (on GPIO P4.31) mode as the chip select, address pin A19 for ALE, address pin A21 for CLE, and GPIO P2.21 for monitoring the ready/busy status. Is you board using these exact same pins? One more item to note is that the muxing for the NAND pins is not setup in the NAND driver, it's setup in the pins configuration (http://git.lpclinux.com/?p=uboot-2011.06-lpc17xx.git;a=blob;f=board/nxp/ea1788/pins.c;h=55a300ea5c16...) file, which is also board specific.
/*
* EA1788 board setup with CS1 as chip select. ALE uses A19, CLE uses A21,
* and NAND RDY/BUSY is read on GPIO P2.21. CS1 is controlled as a GPIO
* instead of a CS on GPIO P4.31 to lock the CS state during NAND transfers.
*/
#define NAND_ALE_OFFS   (1 << 19)
#define NAND_CLE_OFFS   (1 << 20)

thanks,
Kevin
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