Minimum connections to talk to LPC4330 (100BGA) via SWD

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Minimum connections to talk to LPC4330 (100BGA) via SWD

1,287件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Zuofu on Thu Jul 11 23:04:12 MST 2013

Hi,


I have designed a simple 2 layer board with a minimum of connections for the LPC4330. It basically only has USB, SD, and a couple of SGPIO...


 


However, when I build the board, I cannot access the chip via SWD (using uLINK-ME). My understanding is that only SWDIO/SWCLK and !RESET have to be connected to the 10-pin header (as well as all VCC/GND lines, and DBGEN pulled high). The chip draws a reasonable 10mA or so (running no code), which leads me to suggest at least power and ground are not shorting and that some of the power balls should be connected. I've attached my (somewhat disorganized) schematic. The debugging stuff is on the lower right. Am I missing something? Is it necessary to connect TDI even if using SWD? I noticed that the user manual for the LPC4330 has pullups on the SWD pins, but the LPC4330-Xplorer schematic does not...is there something else I'm missing?


Thanks

Original Attachment has been moved to: schematic.zip

ラベル(1)
0 件の賞賛
返信
2 返答(返信)

1,218件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by TheFallGuy on Thu Jul 16 22:59:39 MST 2015
Look at this FAQ
https://www.lpcware.com/content/faq/lpcxpresso/debug-design
0 件の賞賛
返信

1,218件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by malikamalshan@hotmail.com on Thu Jul 16 22:28:23 MST 2015
Hi,
I am planning to use something similar. did you manage to get it working yet? or is there any update for the schematic?
0 件の賞賛
返信