I have observed different behavior between LPC1853 MCUs built in different years. They are all revision 'A'. I will list two MCUs here for comparison:
1) LPC1853FET256 ESD15300A
2) LPC1853FET256 ESD17010A
The first one was manufactured in 2015 week 30, and the second one in 2017 week 1. The difference in behavior is with regards to GPIO P5_3 (T8). There might be other GPIO that is affected, but I am focusing on this pin for this discussion. On the first MCU, when LPC_RGU->RESET_CTRL0's bit 1 (PERIPH_RST) is set, T8 is not affected. On the second MCU, when LPC_RGU->RESET_CTRL0's bit 1 is set, T8 is pulled low by the MCU.
Looking at the errata (ES_LPC185X_3X_2X_1X_FLASH) for this MCU, RESET.2 states this:
Problem:
On the LPC18xx, PERIPH_RST is not functional. CMSIS call NVIC_SystemReset() uses
PERIPH_RST internally and is also non-functional.
Work-around:
There is no work-around. To reset the entire chip, use the CORE_RST instead of using
CMSIS call NVIC_SystemReset() or PERIPH_RST.
My first question is:
What does 'not functional' mean? I could see the MCU reset when PERIPH_RST is set. There is a difference in behavior depending on the manufacture date though.
Here is Table 154 from UM10430:
My second question:
If I do not want any GPIO to change state during MCU reset, could I use MASTER_RST?
The errata (RESET.1) also says to not use it:
Problem:
On the LPC18xx, MASTER_RST and M3_RST are not functional.
Work-around:
There is no work-around. To reset the entire chip use the CORE_RST instead of using
MASTER_RST or M3_RST.
My third question: Is PERIPH_RST or MASTER_RST safe to use in any revision 'A' LPC1853?
RESET.1 in the errata also says MASTER_RST is not functional. I hope someone could help clarify what this means, as I observed the MCU reset without changing the state of T8 when MASTER_RST is used on both the above MCUs.
Any help would be greatly appreciated.
