Content originally posted in LPCWare by S.Kojima on Sun May 08 19:36:33 MST 2016
Dear fellows,
I'm trying to use LPC824's DMAC triggered by SCT's DREQ signal.
But, no in success yet.
The description for the DMAC channel is ...
Destination is one of SCT's MATCHREL[n].L, a fixed address
Source in ROM two different values to update MATCH value alternatively by those two values.
So, SRCINC=1 while DSTINC=0.
To repeat this update sequence, the next field of the descriptor points back itself.
Of course, PERIPHREQEN=0, HWTRIGEN=1 to accept trigger, disabling peripheral request.
TRIGBURST=0 for step-by-step sequence at every trigger.
Unexpected behavior that I'm watching now is...
once the DMA ch is triggered, it starts updating sequence, but at unexpected update timing
regardless of the hardware trigger timing and sequence never stops until the DMA channel is disabled.
Before supplying hardware trigger, I tested software triggering thru uVision debuger.
PERIPHREQEN=0, HWTRIGEN=0 to disable any hardware req and trig.
Descriptor setting is as same as above.
After enabling that DMA ch, I give a trigger to that DMA ch thru SETTRIG register.
Then, that DMA ch starts working thru the descriptor sequence. But, never stops.
The descriptor execution and each DMA transactions are correctly made as I coded.
The only strange thing is the response after accepting the first trigger.
That DMA ch seems doing the transfer activity at full-speed even I gave just one trigger.
Maybe, this is the essential cause that I've experienced with HW-trigger by SCT.
I think I should solve this simpler one first, before I go forth with HW-triggering.
But, I have no idea what is wrong.
Regards,
