I have written some pulse control software for LPC4337 @ 200MHz. Some code is in M0 but of no consequence. Most of the code is in M4.
M4:-
It uses 4 timers (0-3), and 4 Match compares per timer. 1us timer clock
The Matches generate interrupts, and those interrupts check the IR[] to find the source, clear that bit, and manually control an individual GPIO output.
Something strange is happening. At random intervals (anywhere from 18 seconds to 20 mins), Timer 2 Match 3 INT gets missed! ALL OTHER TIMER INTS ARE OK. It will miss a single INT, then next time the compare register is set the INT works fine.
I cannot explain it, all INTs use similar code, and the code that sets the compare registers is similar.
So, Timer 0 Match 0-3 OK
Timer 1 Match 0-3 OK
Timer 2 Match 0 OK, 1 OK, 2 OK, 3 Glitches (IR[2] & 0x08)
Timer 3 Match 0-3 OK
SCT is unused
-Sam
Hi,
I do a quick test with LPCXpresso4337 board Timer2 match 3 at [timers] of [lpcopen_3_02_keil_iar_xpresso4337] software package.
I don't find you mentioned issue.
Could you only do the test with Timer2 Match3, if there still with the same issue?
I attached my test code for your reference.
best regards,
Mike
Trigger software (activated by an external trigger)
if (Number == 0 && PipNum == 1)
{
LPC_GPIO_PORT->SET[3] |= 0x00000020; LPC_TIMER2->MR[0] = LPC_TIMER2->TC + Want;
LPC_TIMER2->IR |= 1; // Clear Flag
Number ++;
if (Number >= 6)
Number = 0;
}
else if (Number == 1 && PipNum == 2)
{
LPC_GPIO_PORT->SET[3] |= 0x00000010; LPC_TIMER2->MR[1] = LPC_TIMER2->TC + Want;
LPC_TIMER2->IR |= 2; // Clear Flag
Number ++;
if (Number >= 6)
Number = 0;
}
else if (Number == 2 && PipNum == 3)
{
LPC_GPIO_PORT->SET[2] |= 0x00000010; LPC_TIMER2->MR[2] = LPC_TIMER2->TC + Want;
LPC_TIMER2->IR |= 4; // Clear Flag
Number ++;
if (Number >= 6)
Number = 0;
}
else if (Number == 3 && PipNum == 4)
{
LPC_GPIO_PORT->SET[5] |= 0x00010000; LPC_TIMER2->MR[3] = LPC_TIMER2->TC + Want;
LPC_TIMER2->IR |= 8; // Clear Flag
Number ++;
if (Number >= 6)
Number = 0;
}
else if (Number == 4 && PipNum == 5)
{
LPC_GPIO_PORT->SET[2] |= 0x00004000; LPC_TIMER3->MR[0] = LPC_TIMER3->TC + Want;
LPC_TIMER3->IR |= 1; // Clear Flag
Number ++;
if (Number >= 6)
Number = 0;
}
else if (Number == 5 && PipNum == 6)
{
LPC_GPIO_PORT->SET[2] |= 0x00000004; LPC_TIMER3->MR[1] = LPC_TIMER3->TC + Want;
LPC_TIMER3->IR |= 2; // Clear Flag
Number ++;
if (Number >= 6)
Number = 0;
}
}
Timer INT routines:-
void TIMER2_IRQHandler(void) // Switch off solenoids 1-4
{
asm("CPSID i"); // Disable all interrupts
if ((LPC_TIMER2->IR & 0x01) != 0)
{
LPC_TIMER2->IR |= 1; // Clear Flag
if (oneshot == 1)
{
oneshot = 2;
LPC_GPIO_PORT->CLR[3] |= 0x00000010;
LPC_GPIO_PORT->CLR[2] |= 0x00000010;
LPC_GPIO_PORT->CLR[5] |= 0x00010000;
LPC_GPIO_PORT->CLR[2] |= 0x00004000;
LPC_GPIO_PORT->CLR[2] |= 0x00000004;
LPC_GPIO_PORT->CLR[2] |= 0x00000002;
LPC_GPIO_PORT->CLR[2] |= 0x00000001;
}
LPC_GPIO_PORT->CLR[3] |= 0x00000020;
}
if ((LPC_TIMER2->IR & 0x02) != 0)
{
LPC_TIMER2->IR |= 2; // Clear Flag
LPC_GPIO_PORT->CLR[3] |= 0x00000010;
}
if ((LPC_TIMER2->IR & 0x04) != 0)
{
LPC_TIMER2->IR |= 4; // Clear Flag
LPC_GPIO_PORT->CLR[2] |= 0x00000010;
}
if ((LPC_TIMER2->IR & 0x08) != 0)
{
LPC_TIMER2->IR |= 8; // Clear Flag
LPC_GPIO_PORT->CLR[5] |= 0x00010000;
}
LPC_TIMER2->IR |= 0xF0;
asm("CPSIE i"); // Enable all interrupts
}
//
//
//
void TIMER3_IRQHandler(void)
{
asm("CPSID i"); // Disable all interrupts
if ((LPC_TIMER3->IR & 0x01) != 0)
{
LPC_TIMER3->IR = 1; // Clear Flag
LPC_GPIO_PORT->CLR[2] |= 0x00004000;
}
if ((LPC_TIMER3->IR & 0x02) != 0)
{
LPC_TIMER3->IR = 2; // Clear Flag
LPC_GPIO_PORT->CLR[2] |= 0x00000004;
}
if ((LPC_TIMER3->IR & 0x04) != 0)
{
LPC_TIMER3->IR = 4; // Clear Flag
LPC_GPIO_PORT->CLR[2] |= 0x00000002;
}
if ((LPC_TIMER3->IR & 0x08) != 0)
{
LPC_TIMER3->IR = 8; // Clear Flag
LPC_GPIO_PORT->CLR[2] |= 0x00000001;
}
// LPC_TIMER3->IR |= 0xF0;
asm("CPSIE i"); // Enable all interrupts
}
Hi Sam,
From the description, you are using Timer module for match compares, not State Configurable Timer (SCT).
Could you provide the test code for Timer 2? I could do a onsite test.
Have a great day,
Mike
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