Content originally posted in LPCWare by capiman on Sun Nov 24 05:46:09 MST 2013
Hi,
from user manual:
SSP (base address 0x4008 8000 (SSP0), 0x4003 0000 (SSP1), 0x400A C000 (SSP2))
I assume your address SSP0 was a cut&paste error in the posting?
What happens when you write? Do you get into some fault handler (e.g. hard fault)?
What values do you write into CR0, CR1, CPSR to initialize the interface?
Have you seen chapter 21.1:
The three SSP interfaces, SSP0, SSP1, and SSP2 are configured using the following registers:
1. Power: In the PCONP register (Table 16), set bit PCSSP0 to enable SSP0 and bit PCSSP1 to enable SSP1.
Remark: On reset, SSP interfaces 0 and 1 are enabled (PCSSP0/1 = 1), while SSP2 is disabled (PCSSP2 = 0).
2. Peripheral clock: The SSPs operate from the common PCLK that clocks both the bus interface
and functional portion of most APB peripherals. See Section 3.3.21. In master mode, the clock must be scaled down (see Section 21.6.5).
3. Pins: Select the SSP pins and pin modes through the relevant IOCON registers (Section 7.4.1).
4. Interrupts: Interrupts are enabled in the SSP0IMSC register for SSP0 and SSP1IMSC register for SSP1 Table 482.
Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register, see Table 48.
5. Initialization: There are two control registers for each of the SSP ports to be configured:
SSP0CR0 and SSP0CR1 for SSP0, SSP1CR0 and SSP1CR1 for SSP1,
SSP2CR0 and SSP2CR1 for SSP2. See Section 21.6.1 and Section 21.6.2.
6. DMA: The Rx and Tx FIFOs of the SSP interfaces can be connected to the GPDMA
controller (see Section 21.6.10). For GPDMA system connections, see Table 685.
Have you done at least steps 1, 2, 3 and 5? 4 only if you use interrupt, 6 if you use DMA.
Best regards,
Martin
