LPC1778 SWD SWCLK Pull Up or Pull Down

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LPC1778 SWD SWCLK Pull Up or Pull Down

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by MikeSimmonds on Thu Nov 06 23:38:33 MST 2014
Hi we are about to make revised PCB for our custom 1778 board to fix errors/problems.

However, before the lasted PCB is finalised, I have noticed a contradiction in  the requirements
for the SWD SWCLK signal.

In this FAQ "Design Considerations for Debug" at http://www.lpcware.com/content/faq/lpcxpresso/debug-design
it shows a pull DOWN on the clock line.

JTAG Mode SWD Mode Signal Notes
TCK SWCLK Clock into the core Use 10K-100K Ohm pull-down resistor to GND


In the latest UM10470 for LPC178x/7x Fig 176 "Cortex Debug Connector" it shows a pull UP
[Also in UM10503]

The schematic for the e.g the MCB1700 board uses a pull down.

Our board in revisions A and B use a pull down and debug certainly works with the original LPC-Link
and with LPC-Link2 (Redlink)

So what is the OFFICIAL requirements.
Is it the user manual(s) or the FAQ in error?

And does it really matter after all is said and done?

Regards Mike

NXP: If you could answer promptly, as we need to get these PCB's made soonest.





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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by IanB on Wed Nov 12 11:16:21 MST 2014
Unlike Mike, I'm using a device which shares its serial wire pins with GPIO. If the pull-up is enabled in IOCON as its default condition out of reset, doesn't it have a pull-up? Could you please clarify.

If I were to add a pull-down on SWCLK, and just happened to use a value which sinks the same amount of current that the internal pull-up sources, then it will be biassed right in the middle - just where it is most vulnerable to noise, and just where it will make the following stage draw current from the supply.

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oliviermartin
Contributor I
Unlike Mike, I'm using a device which shares its serial wire pins with GPIO. If the pull-up is enabled in IOCON as its default condition out of reset, doesn't it have a pull-up? Could you please clarify.

This message is a bit old but I will reply it as it might help other people and I asked myself the same question tonight. Here is the answer from Design Considerations for Debug :

Some MCUs do not include internal pull-up or pull-down resistors on JTAG/SWD pins. You  will need to review the datasheet for the specific MCU being used to confirm. Where internal resistors are not provided, these should be added externally onto your board as detailed above. You may use resistors between 10K and 100K for these signals. This will prevent the signals from floating when they are not connected to anything. Failure to do this will lead to, at best, unreliable debug connections, or more likely no ability to debug at all.

 

If an internal resistor is provided for a pin by the MCU, then an external resistor  is not required for that pin. But if external resistor is provided in such cases, then it must match that provided internally by the MCU.

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oliviermartin
Contributor I

Hmm, actually NXP Documentation does not agree with above NXP statement: "But if external resistor is provided in such cases, then it must match that provided internally by the MCU."

In the LPC11U6x User Manual and Data sheet it is said SWDIO and SWCLK have an internal pull-up for SWDIO and pull-down for SWCLK by default. But both documents contain a diagram that shows the recommendation to add a pull-up and pull-down resistors. And the value of these resistors do not necessary match the internal MCU...

So what should be done for LPC11U6x?

LPC11U6x-SWD.png

LPC11U6X-fig44.png

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by MikeSimmonds on Wed Nov 12 10:05:03 MST 2014
Thanks for the clarification.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by lpcxpresso-support on Wed Nov 12 01:52:23 MST 2014
For SWCLK, a pull-down is recommended, although you can alternatively use a pull-up. The main thing is that it does not float.

[We've added a note to the Design Considerations for Debug FAQ for this, and will pass on the request for this to be made clearer in future MCU user manuals.]

@IanB - I would also like to emphasis that not putting the recommended pull-ups/pull-downs on the debug lines is at best likely to lead to unreliable debug connections.

Regards,
LPCXpresso Support
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by MikeSimmonds on Wed Nov 12 01:33:00 MST 2014

Quote: NXP_Paul
Mike
I think that this pin should have a pull-down since this is what I see on all the demo boards, and your board works with this configuration as well.
I will try to confirm this, but I probably can't get you an answer today.

Paul



Hi Paul, did you manage to confirm this?

Mike
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by IanB on Sat Nov 08 14:27:53 MST 2014
Fair enough - and when NXP answers your question, perhaps they'd like to comment on the pull-up pull-down conflict for the LPC11xx devices.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by MikeSimmonds on Sat Nov 08 05:20:34 MST 2014
The LPC1778 however has dedicated JTAG/SWD lines.
The user manual states internal pullups for !TRST, TDI and TMS (SWIO) but nothing for TDO or TCK (SWCLK).

So my question stands.

Mike.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by IanB on Sat Nov 08 04:44:13 MST 2014
I have used several LPC devices, and have not used pull-ups or pull-downs on the SWD lines.

If you look at the relevant section in IOCON the pins both start up with a pull-up enabled. The pull-ups on these devices are specified between 15µA and 85µA, so are equivalent to having a pull-up resistor between 39k and 220k. It seems a bit daft to add a pull-down resistor - it's a recipe to set the input voltage at some intermediate value where it is more vulnerable to noise, and if it is like any other CMOS gate, cause the input devices to draw current from the supply.

SWCLK is a single direction signal, so is always driven from the programmer.
SWDIO is bidirectional, and if you watch it on a 'scope you can see that it slowly floats upwards in the gaps when it is driven by neither end.

One thing did flummox me for a while. On a LPC12xx, when the power to the board is removed, there will be voltage on Vdd that is supplied through the SWCLK/SWDIO pins, but on an LCP11xx there isn't. I eventually realised why - the LPC11xx has 5V tolerant inputs, and the LPC12xx doesn't. That means the LPC12xx has diodes between inputs and Vdd, and the LPC11xx doesn't. The LPC12xx gets supplied from SWCLK/SWDIO through its protection diodes.

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by MikeSimmonds on Fri Nov 07 11:30:35 MST 2014
Thanks for that.
I have a few days grace [management level red-tape for the accountants].

I was wondering:
Does it matter which way the pin is tied (as long as it is one or the other) because any
adapter will be actively driving the pin, and if no adapter is fitted the line will not be floating.

I seem to remember that a hardware engineer once told me that a pull down on an
unused input is better in that there is a lower leakage current (whatever that might be).

So really (if the above is valid) the question is why the difference between the FAQ and the UM(s).

Still, it will be good to have a definitive ruling form the actual silicon implementers.

Regards, Mike
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by NXP_Paul on Fri Nov 07 11:10:20 MST 2014
Mike
I think that this pin should have a pull-down since this is what I see on all the demo boards, and your board works with this configuration as well.
I will try to confirm this, but I probably can't get you an answer today.

Paul
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